forked from OSchip/llvm-project
[mips] Fix compact branch hazard detection
In certain cases it is possible that transient instructions such as %reg = IMPLICIT_DEF as a single instruction in a basic block to reach the MipsHazardSchedule pass. This patch teaches MipsHazardSchedule to properly look through such cases. Reviewers: vkalintiris, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D27209 llvm-svn: 289529
This commit is contained in:
Simon Dardis
parent
2d9adbf524
commit
43b5ce492d
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@ -91,20 +91,44 @@ FunctionPass *llvm::createMipsHazardSchedule() {
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return new MipsHazardSchedule();
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}
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// Find the next real instruction from the current position.
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static Iter getNextMachineInstr(Iter Position) {
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// Find the next real instruction from the current position in current basic
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// block.
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static Iter getNextMachineInstrInBB(Iter Position) {
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Iter I = Position, E = Position->getParent()->end();
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I = std::find_if_not(I, E, [](const Iter &Insn) { return Insn->isTransient(); });
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assert(I != E);
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I = std::find_if_not(I, E,
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[](const Iter &Insn) { return Insn->isTransient(); });
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return I;
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}
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// Find the next real instruction from the current position, looking through
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// basic block boundaries.
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static Iter getNextMachineInstr(Iter Position) {
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if (std::next(Position) == Position->getParent()->end()) {
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const MachineBasicBlock * MBB = (&*Position)->getParent();
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for (auto *Succ : MBB->successors()) {
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if (MBB->isLayoutSuccessor(Succ)) {
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Iter I = Succ->begin();
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Iter Next = getNextMachineInstrInBB(I);
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if (Next == Succ->end()) {
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return getNextMachineInstr(I);
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} else {
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return I;
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}
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}
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}
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llvm_unreachable("Should have identified the end of the function earlier!");
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}
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return getNextMachineInstrInBB(Position);
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}
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bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) {
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const MipsSubtarget *STI =
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&static_cast<const MipsSubtarget &>(MF.getSubtarget());
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// Forbidden slot hazards are only defined for MIPSR6.
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// Forbidden slot hazards are only defined for MIPSR6 but not microMIPSR6.
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if (!STI->hasMips32r6() || STI->inMicroMipsMode())
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return false;
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@ -118,27 +142,23 @@ bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) {
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if (!TII->HasForbiddenSlot(*I))
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continue;
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bool InsertNop = false;
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// Next instruction in the basic block.
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if (std::next(I) != FI->end() &&
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!TII->SafeInForbiddenSlot(*getNextMachineInstr(std::next(I)))) {
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InsertNop = true;
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Iter Inst;
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bool LastInstInFunction =
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std::next(I) == FI->end() && std::next(FI) == MF.end();
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if (!LastInstInFunction) {
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if (std::next(I) != FI->end()) {
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// Start looking from the next instruction in the basic block.
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Inst = getNextMachineInstr(std::next(I));
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} else {
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// Next instruction in the physical successor basic block.
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for (auto *Succ : FI->successors()) {
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if (FI->isLayoutSuccessor(Succ) &&
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getNextMachineInstr(Succ->begin()) != Succ->end() &&
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!TII->SafeInForbiddenSlot(*getNextMachineInstr(Succ->begin()))) {
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InsertNop = true;
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break;
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}
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Inst = getNextMachineInstr(I);
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}
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}
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if (InsertNop) {
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if (LastInstInFunction || !TII->SafeInForbiddenSlot(*Inst)) {
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Changed = true;
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MIBundleBuilder(&*I).append(
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BuildMI(MF, I->getDebugLoc(), TII->get(Mips::NOP)));
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MIBundleBuilder(&*I)
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.append(BuildMI(MF, I->getDebugLoc(), TII->get(Mips::NOP)));
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NumInsertedNops++;
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}
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}
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@ -0,0 +1,158 @@
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# RUN: llc -march=mips64 -mcpu=mips64r6 -start-after=block-placement -o - %s | FileCheck %s
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# Check that MipsHazardSchedule sees through basic blocks with transient instructions.
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# The mir code in this file isn't representative of the llvm-ir.
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--- |
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; ModuleID = 'test.ll'
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source_filename = "test.c"
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target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
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target triple = "mips64-img-linux-gnu"
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; Function Attrs: nounwind
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define i32 @f(i32 signext %a) {
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entry:
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%retval = alloca i32, align 4
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%a.addr = alloca i32, align 4
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store i32 %a, i32* %a.addr, align 4
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%0 = load i32, i32* %a.addr, align 4
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%cmp = icmp sgt i32 %0, 5
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br i1 %cmp, label %if.then, label %if.else
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if.then: ; preds = %entry
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%1 = load i32, i32* %a.addr, align 4
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%2 = load i32, i32* %a.addr, align 4
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%add = add nsw i32 %1, %2
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store i32 %add, i32* %retval, align 4
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br label %return
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if.else: ; preds = %entry
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%3 = load i32, i32* %a.addr, align 4
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%call = call i32 @g(i32 signext %3)
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store i32 %call, i32* %retval, align 4
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br label %return
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return: ; preds = %if.else, %if.then
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%4 = load i32, i32* %retval, align 4
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ret i32 %4
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}
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declare i32 @g(i32 signext)
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**)
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!llvm.ident = !{!0}
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!0 = !{!"clang version 4.0.0 "}
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...
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---
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# CHECK-LABEL: f:
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# CHECK: bgtzc
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# CHECK-NEXT: nop
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# CHECK: bltzc
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# CHECK-NEXT: nop
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# CHECK: blezc
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name: f
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alignment: 3
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%a0_64' }
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- { reg: '%t9_64' }
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calleeSavedRegisters: [ '%fp', '%gp', '%ra', '%d12', '%d13', '%d14', '%d15',
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'%f24', '%f25', '%f26', '%f27', '%f28', '%f29',
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'%f30', '%f31', '%fp_64', '%f_hi24', '%f_hi25',
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'%f_hi26', '%f_hi27', '%f_hi28', '%f_hi29', '%f_hi30',
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'%f_hi31', '%gp_64', '%ra_64', '%s0', '%s1', '%s2',
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'%s3', '%s4', '%s5', '%s6', '%s7', '%d24_64', '%d25_64',
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'%d26_64', '%d27_64', '%d28_64', '%d29_64', '%d30_64',
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'%d31_64', '%s0_64', '%s1_64', '%s2_64', '%s3_64',
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'%s4_64', '%s5_64', '%s6_64', '%s7_64' ]
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 32
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offsetAdjustment: 0
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maxAlignment: 8
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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stack:
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- { id: 0, name: retval, offset: -28, size: 4, alignment: 4 }
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- { id: 1, name: a.addr, offset: -32, size: 4, alignment: 4 }
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- { id: 2, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '%ra_64' }
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- { id: 3, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '%fp_64' }
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- { id: 4, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '%gp_64' }
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body: |
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bb.0.entry:
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successors: %bb.1.if.then(0x40000000), %bb.5.if.else(0x40000000)
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liveins: %a0_64, %t9_64, %ra_64, %fp_64, %gp_64
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%sp_64 = DADDiu %sp_64, -32
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CFI_INSTRUCTION def_cfa_offset 32
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SD killed %ra_64, %sp_64, 24 :: (store 8 into %stack.2)
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SD killed %fp_64, %sp_64, 16 :: (store 8 into %stack.3)
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SD killed %gp_64, %sp_64, 8 :: (store 8 into %stack.4)
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CFI_INSTRUCTION offset %ra_64, -8
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CFI_INSTRUCTION offset %fp_64, -16
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CFI_INSTRUCTION offset %gp_64, -24
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CFI_INSTRUCTION def_cfa_register %fp_64
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%at_64 = LUi64 @f
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%v0_64 = DADDu killed %at_64, %t9_64
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SW %a0, %sp_64, 0 :: (store 4 into %ir.a.addr)
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BGTZC %a0, %bb.5.if.else, implicit-def %at
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bb.1.if.then:
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successors: %bb.6.return(0x40000000), %bb.2.if.then(0x40000000)
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liveins: %a0
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BLTZC %a0, %bb.6.return, implicit-def %at
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bb.2.if.then:
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successors: %bb.3.if.else(0x80000000)
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%t8 = IMPLICIT_DEF
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bb.3.if.else:
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successors: %bb.6.return(0x40000000), %bb.4.if.else(0x40000000)
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liveins: %t8
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BLEZC %t8, %bb.6.return, implicit-def %at
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bb.4.if.else:
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successors: %bb.6.return(0x80000000)
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liveins: %t8
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%at = LW %sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
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%at = ADDu killed %at, %t8
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SW killed %at, %sp_64, 4 :: (store 4 into %ir.retval)
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J %bb.6.return, implicit-def dead %at
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bb.5.if.else:
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successors: %bb.6.return(0x80000000)
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liveins: %v0_64
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%gp_64 = DADDiu killed %v0_64, @f
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%a0_64 = LW64 %sp_64, 0 :: (dereferenceable load 4 from %ir.a.addr)
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%t9_64 = LD %gp_64, @g :: (load 8 from call-entry @g)
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JALR64Pseudo %t9_64, csr_n64, implicit-def dead %ra, implicit %a0_64, implicit %gp_64, implicit-def %sp, implicit-def %v0
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SW killed %v0, %sp_64, 4 :: (store 4 into %ir.retval)
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bb.6.return:
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%v0 = LW %sp_64, 4 :: (dereferenceable load 4 from %ir.retval)
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%gp_64 = LD %sp_64, 8 :: (load 8 from %stack.4)
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%fp_64 = LD %sp_64, 16 :: (load 8 from %stack.3)
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%ra_64 = LD %sp_64, 24 :: (load 8 from %stack.2)
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%sp_64 = DADDiu %sp_64, 32
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PseudoReturn64 %ra_64
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...
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