forked from OSchip/llvm-project
[InstCombine] add test for faulty cttz fold (PR45762); NFC
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@ -1,7 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -instcombine -S < %s | FileCheck %s
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declare i3 @llvm.cttz.i3(i3, i1)
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declare i32 @llvm.cttz.i32(i32, i1 immarg)
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declare i32 @llvm.ctlz.i32(i32, i1 immarg)
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declare i64 @llvm.cttz.i64(i64, i1 immarg)
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@ -217,3 +217,33 @@ define <2 x i32> @select_clz_to_ctz_vec_with_undef(<2 x i32> %a) {
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%cond = select <2 x i1> %tobool, <2 x i32> %lz, <2 x i32> %sub1
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ret <2 x i32> %cond
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}
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define i4 @PR45762(i3 %x4) {
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; CHECK-LABEL: @PR45762(
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; CHECK-NEXT: [[T4:%.*]] = call i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 true), !range !2
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; CHECK-NEXT: [[T7:%.*]] = zext i3 [[T4]] to i4
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; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl i4 1, [[T7]]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i3 [[X4]], 0
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; CHECK-NEXT: [[NARROW:%.*]] = select i1 [[TMP1]], i3 0, i3 [[T4]]
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; CHECK-NEXT: [[UMUL_23:%.*]] = zext i3 [[NARROW]] to i4
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; CHECK-NEXT: [[SEL_71:%.*]] = shl i4 [[ONE_HOT_16]], [[UMUL_23]]
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; CHECK-NEXT: ret i4 [[SEL_71]]
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;
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%t4 = call i3 @llvm.cttz.i3(i3 %x4, i1 false)
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%t5 = icmp eq i3 %x4, 0
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%t6 = select i1 %t5, i3 3, i3 %t4
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%t7 = zext i3 %t6 to i4
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%one_hot_16 = shl i4 1, %t7
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%t8 = lshr i4 %one_hot_16, 0
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%bit_slice_61 = trunc i4 %t8 to i1
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%t9 = lshr i4 %one_hot_16, 1
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%bit_slice_62 = trunc i4 %t9 to i1
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%t10 = lshr i4 %one_hot_16, 2
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%bit_slice_64 = trunc i4 %t10 to i1
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%t11 = or i1 %bit_slice_61, %bit_slice_62
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%or_69 = or i1 %t11, %bit_slice_64
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%umul_23 = mul i4 %one_hot_16, %one_hot_16
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%t12 = icmp eq i1 %or_69, false
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%sel_71 = select i1 %t12, i4 %one_hot_16, i4 %umul_23
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ret i4 %sel_71
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}
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