forked from OSchip/llvm-project
m68k: Support bit shifts on 64-bit integers
As per https://bugs.llvm.org/show_bug.cgi?id=52119. Reviewed By: myhsu Differential Revision: https://reviews.llvm.org/D111497
This commit is contained in:
Annika
Sheng
parent
73e585e44d
commit
43a1756a5d
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@ -101,6 +101,9 @@ M68kTargetLowering::M68kTargetLowering(const M68kTargetMachine &TM,
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setOperationAction(OP, MVT::i32, Expand);
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}
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for (auto OP : {ISD::SHL_PARTS, ISD::SRA_PARTS, ISD::SRL_PARTS})
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setOperationAction(OP, MVT::i32, Custom);
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// Add/Sub overflow ops with MVT::Glues are lowered to CCR dependences.
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for (auto VT : {MVT::i8, MVT::i16, MVT::i32}) {
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setOperationAction(ISD::ADDC, VT, Custom);
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@ -1354,6 +1357,12 @@ SDValue M68kTargetLowering::LowerOperation(SDValue Op,
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return LowerVASTART(Op, DAG);
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case ISD::DYNAMIC_STACKALLOC:
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return LowerDYNAMIC_STACKALLOC(Op, DAG);
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case ISD::SHL_PARTS:
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return LowerShiftLeftParts(Op, DAG);
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case ISD::SRA_PARTS:
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return LowerShiftRightParts(Op, DAG, true);
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case ISD::SRL_PARTS:
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return LowerShiftRightParts(Op, DAG, false);
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}
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}
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@ -3239,6 +3248,102 @@ SDValue M68kTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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return DAG.getMergeValues(Ops, DL);
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}
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SDValue M68kTargetLowering::LowerShiftLeftParts(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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SDValue Lo = Op.getOperand(0);
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SDValue Hi = Op.getOperand(1);
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SDValue Shamt = Op.getOperand(2);
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EVT VT = Lo.getValueType();
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// if Shamt - register size < 0: // Shamt < register size
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// Lo = Lo << Shamt
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// Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (register size - 1 ^ Shamt))
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// else:
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// Lo = 0
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// Hi = Lo << (Shamt - register size)
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SDValue Zero = DAG.getConstant(0, DL, VT);
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SDValue One = DAG.getConstant(1, DL, VT);
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SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
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SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
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SDValue ShamtMinusRegisterSize =
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DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
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SDValue RegisterSizeMinus1Shamt =
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DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
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SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt);
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SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One);
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SDValue ShiftRightLo =
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DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt);
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SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt);
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SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo);
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SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize);
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SDValue CC =
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DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
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Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
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Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
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return DAG.getMergeValues({Lo, Hi}, DL);
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}
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SDValue M68kTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
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bool IsSRA) const {
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SDLoc DL(Op);
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SDValue Lo = Op.getOperand(0);
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SDValue Hi = Op.getOperand(1);
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SDValue Shamt = Op.getOperand(2);
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EVT VT = Lo.getValueType();
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// SRA expansion:
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// if Shamt - register size < 0: // Shamt < register size
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// Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
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// Hi = Hi >>s Shamt
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// else:
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// Lo = Hi >>s (Shamt - register size);
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// Hi = Hi >>s (register size - 1)
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//
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// SRL expansion:
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// if Shamt - register size < 0: // Shamt < register size
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// Lo = (Lo >>u Shamt) | ((Hi << 1) << (register size - 1 ^ Shamt))
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// Hi = Hi >>u Shamt
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// else:
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// Lo = Hi >>u (Shamt - register size);
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// Hi = 0;
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unsigned ShiftRightOp = IsSRA ? ISD::SRA : ISD::SRL;
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SDValue Zero = DAG.getConstant(0, DL, VT);
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SDValue One = DAG.getConstant(1, DL, VT);
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SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT);
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SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT);
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SDValue ShamtMinusRegisterSize =
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DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
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SDValue RegisterSizeMinus1Shamt =
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DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt);
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SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt);
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SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One);
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SDValue ShiftLeftHi =
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DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt);
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SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi);
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SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt);
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SDValue LoFalse =
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DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize);
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SDValue HiFalse =
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IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero;
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SDValue CC =
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DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT);
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Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
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Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
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return DAG.getMergeValues({Lo, Hi}, DL);
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}
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//===----------------------------------------------------------------------===//
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// DAG Combine
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//===----------------------------------------------------------------------===//
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@ -220,6 +220,8 @@ private:
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool IsVarArg,
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@ -97,6 +97,14 @@ public:
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bool canRealignStack(const MachineFunction &MF) const override;
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Register getFrameRegister(const MachineFunction &MF) const override;
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const TargetRegisterClass *
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getCrossCopyRegClass(const TargetRegisterClass *RC) const override {
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if (RC == &M68k::CCRCRegClass)
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return &M68k::DR32RegClass;
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return RC;
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}
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unsigned getStackRegister() const { return StackPtr; }
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unsigned getBaseRegister() const { return BasePtr; }
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unsigned getGlobalBaseRegister() const { return GlobalBasePtr; }
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@ -230,3 +230,123 @@ define i32 @eoril(i32 %a) nounwind {
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%1 = xor i32 %a, 305419896
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ret i32 %1
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}
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define i64 @lshr64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: lshr64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: movem.l %d2-%d4, (0,%sp) ; 16-byte Folded Spill
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; CHECK-NEXT: move.l (28,%sp), %d3
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; CHECK-NEXT: move.l (16,%sp), %d2
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; CHECK-NEXT: move.l %d3, %d1
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; CHECK-NEXT: add.l #-32, %d1
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; CHECK-NEXT: bmi .LBB18_1
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; CHECK-NEXT: ; %bb.2:
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; CHECK-NEXT: move.l #0, %d0
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; CHECK-NEXT: bra .LBB18_3
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; CHECK-NEXT: .LBB18_1:
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; CHECK-NEXT: move.l %d2, %d0
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; CHECK-NEXT: lsr.l %d3, %d0
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; CHECK-NEXT: .LBB18_3:
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; CHECK-NEXT: move.l %d3, %d4
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; CHECK-NEXT: add.l #-32, %d4
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; CHECK-NEXT: bmi .LBB18_4
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; CHECK-NEXT: ; %bb.5:
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; CHECK-NEXT: lsr.l %d1, %d2
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; CHECK-NEXT: move.l %d2, %d1
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; CHECK-NEXT: bra .LBB18_6
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; CHECK-NEXT: .LBB18_4:
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; CHECK-NEXT: move.l %d3, %d4
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; CHECK-NEXT: eori.l #31, %d4
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; CHECK-NEXT: lsl.l #1, %d2
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; CHECK-NEXT: move.l (20,%sp), %d1
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; CHECK-NEXT: lsl.l %d4, %d2
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; CHECK-NEXT: lsr.l %d3, %d1
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; CHECK-NEXT: or.l %d2, %d1
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; CHECK-NEXT: .LBB18_6:
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; CHECK-NEXT: movem.l (0,%sp), %d2-%d4 ; 16-byte Folded Reload
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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%1 = lshr i64 %a, %b
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ret i64 %1
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}
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define i64 @ashr64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: ashr64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: suba.l #8, %sp
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; CHECK-NEXT: movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill
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; CHECK-NEXT: move.l (24,%sp), %d2
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; CHECK-NEXT: move.l (12,%sp), %d0
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; CHECK-NEXT: move.l %d2, %d3
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; CHECK-NEXT: add.l #-32, %d3
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; CHECK-NEXT: move.l %d2, %d1
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; CHECK-NEXT: add.l #-32, %d1
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; CHECK-NEXT: bmi .LBB19_1
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; CHECK-NEXT: ; %bb.2:
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; CHECK-NEXT: move.l %d0, %d1
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; CHECK-NEXT: asr.l %d3, %d1
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; CHECK-NEXT: bra .LBB19_3
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; CHECK-NEXT: .LBB19_1:
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; CHECK-NEXT: move.l %d2, %d1
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; CHECK-NEXT: eori.l #31, %d1
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; CHECK-NEXT: move.l %d0, %d3
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; CHECK-NEXT: lsl.l #1, %d3
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; CHECK-NEXT: lsl.l %d1, %d3
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; CHECK-NEXT: move.l (16,%sp), %d1
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; CHECK-NEXT: lsr.l %d2, %d1
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; CHECK-NEXT: or.l %d3, %d1
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; CHECK-NEXT: .LBB19_3:
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; CHECK-NEXT: move.l %d2, %d3
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; CHECK-NEXT: add.l #-32, %d3
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; CHECK-NEXT: bmi .LBB19_5
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; CHECK-NEXT: ; %bb.4:
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; CHECK-NEXT: move.l #31, %d2
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; CHECK-NEXT: .LBB19_5:
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; CHECK-NEXT: asr.l %d2, %d0
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; CHECK-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload
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; CHECK-NEXT: adda.l #8, %sp
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; CHECK-NEXT: rts
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%1 = ashr i64 %a, %b
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ret i64 %1
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}
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define i64 @shl64(i64 %a, i64 %b) nounwind {
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; CHECK-LABEL: shl64:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: suba.l #12, %sp
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; CHECK-NEXT: movem.l %d2-%d4, (0,%sp) ; 16-byte Folded Spill
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; CHECK-NEXT: move.l (28,%sp), %d3
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; CHECK-NEXT: move.l (20,%sp), %d2
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; CHECK-NEXT: move.l %d3, %d0
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; CHECK-NEXT: add.l #-32, %d0
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; CHECK-NEXT: bmi .LBB20_1
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; CHECK-NEXT: ; %bb.2:
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; CHECK-NEXT: move.l #0, %d1
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; CHECK-NEXT: bra .LBB20_3
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; CHECK-NEXT: .LBB20_1:
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; CHECK-NEXT: move.l %d2, %d1
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; CHECK-NEXT: lsl.l %d3, %d1
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; CHECK-NEXT: .LBB20_3:
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; CHECK-NEXT: move.l %d3, %d4
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; CHECK-NEXT: add.l #-32, %d4
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; CHECK-NEXT: bmi .LBB20_4
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; CHECK-NEXT: ; %bb.5:
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; CHECK-NEXT: lsl.l %d0, %d2
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; CHECK-NEXT: move.l %d2, %d0
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; CHECK-NEXT: bra .LBB20_6
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; CHECK-NEXT: .LBB20_4:
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; CHECK-NEXT: move.l %d3, %d4
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; CHECK-NEXT: eori.l #31, %d4
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; CHECK-NEXT: lsr.l #1, %d2
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; CHECK-NEXT: move.l (16,%sp), %d0
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; CHECK-NEXT: lsr.l %d4, %d2
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; CHECK-NEXT: lsl.l %d3, %d0
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; CHECK-NEXT: or.l %d2, %d0
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; CHECK-NEXT: .LBB20_6:
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; CHECK-NEXT: movem.l (0,%sp), %d2-%d4 ; 16-byte Folded Reload
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; CHECK-NEXT: adda.l #12, %sp
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; CHECK-NEXT: rts
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%1 = shl i64 %a, %b
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ret i64 %1
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}
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