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[AMDGPU] Add GFX11 flat scratch test coverage

This commit is contained in:
Jay Foad 2022-06-13 13:29:28 +01:00
parent abefed6f97
commit 438c312c03
2 changed files with 1229 additions and 0 deletions
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323
llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
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@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx940 < %s | FileCheck %s -check-prefixes=GFX940-SDAG
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx940 < %s | FileCheck %s -check-prefixes=GFX940-GISEL
; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11-SDAG
; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 < %s | FileCheck %s -check-prefixes=GFX11-GISEL
; Test flat scratch SVS addressing mode with various combinations of alignment
; of soffset, voffset and inst_offset.
@ -41,6 +43,39 @@ define amdgpu_kernel void @soff1_voff1(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff1_voff1:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: soff1_voff1:
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff1 = mul i32 %soff, 1
%a = alloca i8, i32 64, align 4, addrspace(5)
@ -93,6 +128,41 @@ define amdgpu_kernel void @soff1_voff2(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff1_voff2:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: soff1_voff2:
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff1 = mul i32 %soff, 1
%a = alloca i8, i32 64, align 4, addrspace(5)
@ -145,6 +215,41 @@ define amdgpu_kernel void @soff1_voff4(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff1_voff4:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: soff1_voff4:
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff1 = mul i32 %soff, 1
%a = alloca i8, i32 64, align 4, addrspace(5)
@ -197,6 +302,41 @@ define amdgpu_kernel void @soff2_voff1(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff2_voff1:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: soff2_voff1:
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff2 = mul i32 %soff, 2
%a = alloca i8, i32 64, align 4, addrspace(5)
@ -251,6 +391,43 @@ define amdgpu_kernel void @soff2_voff2(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff2_voff2:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: soff2_voff2:
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff2 = mul i32 %soff, 2
%a = alloca i8, i32 64, align 4, addrspace(5)
@ -305,6 +482,43 @@ define amdgpu_kernel void @soff2_voff4(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff2_voff4:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: soff2_voff4:
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 1
; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff2 = mul i32 %soff, 2
%a = alloca i8, i32 64, align 4, addrspace(5)
@ -357,6 +571,41 @@ define amdgpu_kernel void @soff4_voff1(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff4_voff1:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: soff4_voff1:
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff4 = mul i32 %soff, 4
%a = alloca i8, i32 64, align 4, addrspace(5)
@ -411,6 +660,43 @@ define amdgpu_kernel void @soff4_voff2(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff4_voff2:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: soff4_voff2:
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff4 = mul i32 %soff, 4
%a = alloca i8, i32 64, align 4, addrspace(5)
@ -465,6 +751,43 @@ define amdgpu_kernel void @soff4_voff4(i32 %soff) {
; GFX940-GISEL-NEXT: scratch_store_byte v0, v1, off offset:4 sc0 sc1
; GFX940-GISEL-NEXT: s_waitcnt vmcnt(0)
; GFX940-GISEL-NEXT: s_endpgm
;
; GFX11-SDAG-LABEL: soff4_voff4:
; GFX11-SDAG: ; %bb.0: ; %bb
; GFX11-SDAG-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 1
; GFX11-SDAG-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-SDAG-NEXT: v_mov_b32_e32 v2, 2
; GFX11-SDAG-NEXT: v_mov_b32_e32 v3, 4
; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-SDAG-NEXT: s_add_i32 s0, s0, 4
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v1, s0 offset:1 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v2, s0 offset:2 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: scratch_store_b8 v0, v3, s0 offset:4 dlc
; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-SDAG-NEXT: s_endpgm
;
; GFX11-GISEL-LABEL: soff4_voff4:
; GFX11-GISEL: ; %bb.0: ; %bb
; GFX11-GISEL-NEXT: s_load_b32 s0, s[0:1], 0x24
; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v2, 1
; GFX11-GISEL-NEXT: v_mov_b32_e32 v3, 4
; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT: s_lshl_b32 s0, s0, 2
; GFX11-GISEL-NEXT: v_add_nc_u32_e64 v1, s0, 4
; GFX11-GISEL-NEXT: v_add_nc_u32_e32 v0, v1, v0
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 2
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v2, off offset:1 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v1, off offset:2 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: scratch_store_b8 v0, v3, off offset:4 dlc
; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-GISEL-NEXT: s_endpgm
bb:
%soff4 = mul i32 %soff, 4
%a = alloca i8, i32 64, align 4, addrspace(5)

906
llvm/test/CodeGen/AMDGPU/flat-scratch.ll
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