forked from OSchip/llvm-project
parent
b54070745e
commit
437fd559d7
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@ -64,3 +64,8 @@ class InstrItinData<InstrItinClass Class, list<InstrStage> stages> {
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class ProcessorItineraries<list<InstrItinData> iid> {
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list<InstrItinData> IID = iid;
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}
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// NoItineraries - A marker that can be used by processors without schedule
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// info.
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def NoItineraries : ProcessorItineraries<[]>;
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