forked from OSchip/llvm-project
[ARM][LowOverheadLoops] Revert remaining pseudos
ARMLowOverheadLoops would assert a failure if it did not find all the pseudo instructions that comprise the hardware loop. Instead of doing this, iterate through all the instructions of the function and revert any remaining pseudo instructions that haven't been converted. Differential Revision: https://reviews.llvm.org/D65080 llvm-svn: 366691
This commit is contained in:
Sam Parker
parent
25569296c6
commit
4379a40088
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@ -54,6 +54,8 @@ namespace {
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bool ProcessLoop(MachineLoop *ML);
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bool RevertNonLoops(MachineFunction &MF);
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void RevertWhile(MachineInstr *MI) const;
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void RevertLoopDec(MachineInstr *MI) const;
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@ -98,9 +100,15 @@ bool ARMLowOverheadLoops::runOnMachineFunction(MachineFunction &MF) {
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if (!ML->getParentLoop())
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Changed |= ProcessLoop(ML);
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}
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Changed |= RevertNonLoops(MF);
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return Changed;
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}
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static bool IsLoopStart(MachineInstr &MI) {
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return MI.getOpcode() == ARM::t2DoLoopStart ||
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MI.getOpcode() == ARM::t2WhileLoopStart;
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}
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bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
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bool Changed = false;
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@ -111,15 +119,10 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
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LLVM_DEBUG(dbgs() << "ARM Loops: Processing " << *ML);
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auto IsLoopStart = [](MachineInstr &MI) {
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return MI.getOpcode() == ARM::t2DoLoopStart ||
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MI.getOpcode() == ARM::t2WhileLoopStart;
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};
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// Search the given block for a loop start instruction. If one isn't found,
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// and there's only one predecessor block, search that one too.
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std::function<MachineInstr*(MachineBasicBlock*)> SearchForStart =
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[&IsLoopStart, &SearchForStart](MachineBasicBlock *MBB) -> MachineInstr* {
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[&SearchForStart](MachineBasicBlock *MBB) -> MachineInstr* {
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for (auto &MI : *MBB) {
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if (IsLoopStart(MI))
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return &MI;
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@ -165,6 +168,8 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
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Dec = &MI;
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else if (MI.getOpcode() == ARM::t2LoopEnd)
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End = &MI;
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else if (IsLoopStart(MI))
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Start = &MI;
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else if (MI.getDesc().isCall())
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// TODO: Though the call will require LE to execute again, does this
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// mean we should revert? Always executing LE hopefully should be
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@ -190,11 +195,16 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
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break;
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}
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LLVM_DEBUG(if (Start) dbgs() << "ARM Loops: Found Loop Start: " << *Start;
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if (Dec) dbgs() << "ARM Loops: Found Loop Dec: " << *Dec;
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if (End) dbgs() << "ARM Loops: Found Loop End: " << *End;);
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if (!Start && !Dec && !End) {
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LLVM_DEBUG(dbgs() << "ARM Loops: Not a low-overhead loop.\n");
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return Changed;
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} if (!(Start && Dec && End)) {
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report_fatal_error("Failed to find all loop components");
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} else if (!(Start && Dec && End)) {
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LLVM_DEBUG(dbgs() << "ARM Loops: Failed to find all loop components.\n");
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return false;
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}
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if (!End->getOperand(1).isMBB() ||
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@ -216,10 +226,6 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
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Revert = true;
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}
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LLVM_DEBUG(dbgs() << "ARM Loops:\n - Found Loop Start: " << *Start
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<< " - Found Loop Dec: " << *Dec
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<< " - Found Loop End: " << *End);
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Expand(ML, Start, Dec, End, Revert);
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return true;
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}
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@ -379,6 +385,44 @@ void ARMLowOverheadLoops::Expand(MachineLoop *ML, MachineInstr *Start,
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}
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}
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bool ARMLowOverheadLoops::RevertNonLoops(MachineFunction &MF) {
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LLVM_DEBUG(dbgs() << "ARM Loops: Reverting any remaining pseudos...\n");
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bool Changed = false;
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for (auto &MBB : MF) {
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SmallVector<MachineInstr*, 4> Starts;
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SmallVector<MachineInstr*, 4> Decs;
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SmallVector<MachineInstr*, 4> Ends;
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for (auto &I : MBB) {
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if (IsLoopStart(I))
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Starts.push_back(&I);
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else if (I.getOpcode() == ARM::t2LoopDec)
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Decs.push_back(&I);
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else if (I.getOpcode() == ARM::t2LoopEnd)
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Ends.push_back(&I);
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}
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if (Starts.empty() && Decs.empty() && Ends.empty())
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continue;
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Changed = true;
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for (auto *Start : Starts) {
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if (Start->getOpcode() == ARM::t2WhileLoopStart)
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RevertWhile(Start);
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else
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Start->eraseFromParent();
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}
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for (auto *Dec : Decs)
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RevertLoopDec(Dec);
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for (auto *End : Ends)
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RevertLoopEnd(End);
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}
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return Changed;
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}
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FunctionPass *llvm::createARMLowOverheadLoopsPass() {
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return new ARMLowOverheadLoops();
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}
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@ -0,0 +1,170 @@
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# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s --verify-machineinstrs -o - | FileCheck %s
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# CHECK: name: non_loop
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# CHECK: bb.0.entry:
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# CHECK: tBcc %bb.2, 3
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# CHECK: tB %bb.1, 14
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# CHECK: bb.1.not.preheader:
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# CHECK: t2CMPri $lr, 0, 14
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# CHECK: t2Bcc %bb.3, 0
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# CHECK: tB %bb.2
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# CHECK: bb.2.while.body:
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# CHECK: t2CMPri $lr, 0, 14
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# CHECK: t2Bcc %bb.2, 1
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# CHECK: tB %bb.3
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# CHECK: bb.3.while.end:
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--- |
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define void @non_loop(i16* nocapture %a, i16* nocapture readonly %b, i32 %N) {
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entry:
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%cmp = icmp ugt i32 %N, 2
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br i1 %cmp, label %not.preheader, label %while.body
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not.preheader: ; preds = %entry
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%test = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
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br i1 %test, label %while.body, label %while.end
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while.body: ; preds = %while.body, %not.preheader, %entry
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%a.addr.06 = phi i16* [ %incdec.ptr1, %while.body ], [ %a, %entry ], [ %a, %not.preheader ]
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%b.addr.05 = phi i16* [ %incdec.ptr, %while.body ], [ %b, %entry ], [ %b, %not.preheader ]
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%count = phi i32 [ %count.next, %while.body ], [ %N, %entry ], [ %N, %not.preheader ]
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%incdec.ptr = getelementptr inbounds i16, i16* %b.addr.05, i32 1
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%load = load i16, i16* %b.addr.05, align 2
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%incdec.ptr1 = getelementptr inbounds i16, i16* %a.addr.06, i32 1
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store i16 %load, i16* %a.addr.06, align 2
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%count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)
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%cmp1 = icmp ne i32 %count.next, 0
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br i1 %cmp1, label %while.body, label %while.end
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while.end: ; preds = %while.body, %not.preheader
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ret void
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}
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declare i1 @llvm.test.set.loop.iterations.i32(i32) #0
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
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attributes #0 = { noduplicate nounwind }
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attributes #1 = { nounwind }
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...
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---
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name: non_loop
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: false
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 32
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 4, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 5, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 6, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 7, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.1(0x40000000), %bb.2(0x40000000)
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frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$sp = frame-setup tSUBspi $sp, 6, 14, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_offset 32
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tCMPi8 renamable $r2, 3, 14, $noreg, implicit-def $cpsr
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$r3 = tMOVr $r0, 14, $noreg
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$r12 = tMOVr $r1, 14, $noreg
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$lr = tMOVr $r2, 14, $noreg
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tSTRspi killed $r2, $sp, 5, 14, $noreg :: (store 4 into %stack.0)
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tSTRspi killed $r1, $sp, 4, 14, $noreg :: (store 4 into %stack.1)
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tSTRspi killed $r0, $sp, 3, 14, $noreg :: (store 4 into %stack.2)
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tSTRspi killed $r3, $sp, 2, 14, $noreg :: (store 4 into %stack.3)
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t2STRi12 killed $r12, $sp, 4, 14, $noreg :: (store 4 into %stack.4)
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t2STRi12 killed $lr, $sp, 0, 14, $noreg :: (store 4 into %stack.5)
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1.not.preheader:
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successors: %bb.2(0x40000000), %bb.3(0x40000000)
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$r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.2)
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$r1 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.1)
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$r2 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.0)
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$r3 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.0)
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tSTRspi killed $r0, $sp, 2, 14, $noreg :: (store 4 into %stack.3)
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tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.4)
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tSTRspi killed $r2, $sp, 0, 14, $noreg :: (store 4 into %stack.5)
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t2WhileLoopStart killed renamable $r3, %bb.3
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tB %bb.2, 14, $noreg
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bb.2.while.body:
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successors: %bb.2(0x40000000), %bb.3(0x40000000)
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$r0 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.5)
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$r1 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.4)
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$r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.3)
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renamable $r3, renamable $r1 = t2LDRH_POST renamable $r1, 2, 14, $noreg :: (load 2 from %ir.b.addr.05)
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early-clobber renamable $r2 = t2STRH_POST killed renamable $r3, renamable $r2, 2, 14, $noreg :: (store 2 into %ir.a.addr.06)
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$lr = tMOVr killed $r0, 14, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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$r0 = tMOVr $lr, 14, $noreg
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tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.5)
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tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.4)
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tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.3)
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t2LoopEnd killed renamable $lr, %bb.2
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tB %bb.3, 14, $noreg
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bb.3.while.end:
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$sp = tADDspi $sp, 6, 14, $noreg
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tPOP_RET 14, $noreg, def $r7, def $pc
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...
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