forked from OSchip/llvm-project
Incorporated comments from Evan and Chris:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20071203/056043.html http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20071203/056048.html llvm-svn: 44696
This commit is contained in:
Bill Wendling
parent
086b2c4537
commit
4375173ba0
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@ -13,6 +13,7 @@
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "machine-licm"
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#include "llvm/ADT/IndexedMap.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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@ -27,7 +28,6 @@
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include <map>
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using namespace llvm;
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@ -35,9 +35,12 @@ namespace {
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// Hidden options to help debugging
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cl::opt<bool>
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PerformLICM("machine-licm",
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cl::init(false), cl::Hidden);
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cl::init(false), cl::Hidden,
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cl::desc("Perform loop-invariant code motion on machine code"));
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}
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STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loop");
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namespace {
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class VISIBILITY_HIDDEN MachineLICM : public MachineFunctionPass {
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// Various analyses that we use...
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@ -51,7 +54,7 @@ namespace {
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MachineLoop *CurLoop; // The current loop we are working on.
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// Map the def of a virtual register to the machine instruction.
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std::map<unsigned, const MachineInstr*> VRegDefs;
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IndexedMap<const MachineInstr*, VirtReg2IndexFunctor> VRegDefs;
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public:
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static char ID; // Pass identification, replacement for typeid
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MachineLICM() : MachineFunctionPass((intptr_t)&ID) {}
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@ -66,16 +69,23 @@ namespace {
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AU.addRequired<MachineDominatorTree>();
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}
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private:
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/// GatherAllLoops - Get all loops in depth first order.
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/// VisitAllLoops - Visit all of the loops in depth first order and try to
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/// hoist invariant instructions from them.
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///
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void GatherAllLoops(MachineLoop *L, SmallVectorImpl<MachineLoop*> &Loops) {
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void VisitAllLoops(MachineLoop *L) {
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const std::vector<MachineLoop*> &SubLoops = L->getSubLoops();
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for (MachineLoop::iterator
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I = SubLoops.begin(), E = SubLoops.end(); I != E; ++I)
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GatherAllLoops(*I, Loops);
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I = SubLoops.begin(), E = SubLoops.end(); I != E; ++I) {
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MachineLoop *ML = *I;
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Loops.push_back(L);
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// Traverse the body of the loop in depth first order on the dominator
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// tree so that we are guaranteed to see definitions before we see uses.
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VisitAllLoops(ML);
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HoistRegion(DT->getNode(ML->getHeader()));
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}
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HoistRegion(DT->getNode(L->getHeader()));
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}
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/// MapVirtualRegisterDefs - Create a map of which machine instruction
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@ -104,8 +114,12 @@ namespace {
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///
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bool CanHoistInst(MachineInstr &I) const {
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const TargetInstrDescriptor *TID = I.getInstrDescriptor();
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MachineOpCode Opcode = TID->Opcode;
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// Don't hoist if this instruction implicitly reads physical registers or
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// doesn't take any operands.
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if (TID->ImplicitUses || !I.getNumOperands()) return false;
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MachineOpCode Opcode = TID->Opcode;
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return TII->isTriviallyReMaterializable(&I) &&
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// FIXME: Below necessary?
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!(TII->isReturn(Opcode) ||
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@ -137,12 +151,13 @@ namespace {
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Preds.push_back(*I);
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}
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/// MoveInstToBlock - Moves the machine instruction to the bottom of the
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/// predecessor basic block (but before the terminator instructions).
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/// MoveInstToEndOfBlock - Moves the machine instruction to the bottom of
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/// the predecessor basic block (but before the terminator instructions).
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///
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void MoveInstToBlock(MachineBasicBlock *MBB, MachineInstr *MI) {
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void MoveInstToEndOfBlock(MachineBasicBlock *MBB, MachineInstr *MI) {
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MachineBasicBlock::iterator Iter = MBB->getFirstTerminator();
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MBB->insert(Iter, MI);
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++NumHoisted;
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}
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/// HoistRegion - Walk the specified region of the CFG (defined by all
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@ -156,7 +171,7 @@ namespace {
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/// Hoist - When an instruction is found to only use loop invariant operands
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/// that is safe to hoist, this instruction is called to do the dirty work.
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///
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bool Hoist(MachineInstr &MI);
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void Hoist(MachineInstr &MI);
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};
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char MachineLICM::ID = 0;
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@ -188,17 +203,7 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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// Visit all of the instructions of the loop. We want to visit the subloops
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// first, though, so that we can hoist their invariants first into their
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// containing loop before we process that loop.
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SmallVector<MachineLoop*, 16> Loops;
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GatherAllLoops(L, Loops);
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for (SmallVector<MachineLoop*, 8>::iterator
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II = Loops.begin(), IE = Loops.end(); II != IE; ++II) {
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L = *II;
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// Traverse the body of the loop in depth first order on the dominator
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// tree so that we are guaranteed to see definitions before we see uses.
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HoistRegion(DT->getNode(L->getHeader()));
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}
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VisitAllLoops(L);
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}
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return Changed;
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@ -216,7 +221,7 @@ void MachineLICM::MapVirtualRegisterDefs(const MachineFunction &MF) {
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II = MBB.begin(), IE = MBB.end(); II != IE; ++II) {
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const MachineInstr &MI = *II;
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if (MI.getNumOperands() > 0) {
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for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(0);
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if (MO.isRegister() && MO.isDef() &&
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@ -249,9 +254,7 @@ void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
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// Try hoisting the instruction out of the loop. We can only do this if
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// all of the operands of the instruction are loop invariant and if it is
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// safe to hoist the instruction.
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if (Hoist(MI))
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// Hoisting was successful! Remove bothersome instruction now.
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MI.getParent()->remove(&MI);
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Hoist(MI);
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}
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const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
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@ -266,12 +269,6 @@ void MachineLICM::HoistRegion(MachineDomTreeNode *N) {
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/// instruction is hoistable.
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///
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bool MachineLICM::isLoopInvariantInst(MachineInstr &I) {
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const TargetInstrDescriptor *TID = I.getInstrDescriptor();
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// Don't hoist if this instruction implicitly reads physical registers or
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// doesn't take any operands.
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if (TID->ImplicitUses || !I.getNumOperands()) return false;
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if (!CanHoistInst(I)) return false;
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// The instruction is loop invariant if all of its operands are loop-invariant
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@ -287,7 +284,7 @@ bool MachineLICM::isLoopInvariantInst(MachineInstr &I) {
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if (!MRegisterInfo::isVirtualRegister(Reg))
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return false;
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assert(VRegDefs[Reg] && "Machine instr not mapped for this vreg?!");
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assert(VRegDefs[Reg] && "Machine instr not mapped for this vreg?");
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// If the loop contains the definition of an operand, then the instruction
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// isn't loop invariant.
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@ -302,35 +299,34 @@ bool MachineLICM::isLoopInvariantInst(MachineInstr &I) {
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/// Hoist - When an instruction is found to only use loop invariant operands
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/// that is safe to hoist, this instruction is called to do the dirty work.
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///
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bool MachineLICM::Hoist(MachineInstr &MI) {
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if (!isLoopInvariantInst(MI)) return false;
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void MachineLICM::Hoist(MachineInstr &MI) {
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if (!isLoopInvariantInst(MI)) return;
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std::vector<MachineBasicBlock*> Preds;
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// Non-back-edge predecessors.
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FindPredecessors(Preds);
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if (Preds.empty()) return false;
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// Check that the predecessors are qualified to take the hoisted
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// instruction. I.e., there is only one edge from each predecessor, and it's
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// to the loop header.
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for (std::vector<MachineBasicBlock*>::iterator
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I = Preds.begin(), E = Preds.end(); I != E; ++I) {
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MachineBasicBlock *MBB = *I;
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// Either we don't have any predecessors(?!) or we have more than one, which
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// is forbidden.
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if (Preds.empty() || Preds.size() != 1) return;
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// FIXME: We are assuming at first that the basic blocks coming into this
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// loop have only one successor each. This isn't the case in general because
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// we haven't broken critical edges or added preheaders.
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if (MBB->succ_size() != 1) return false;
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assert(*MBB->succ_begin() == CurLoop->getHeader() &&
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"The predecessor doesn't feed directly into the loop header!");
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}
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// Check that the predecessor is qualified to take the hoisted
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// instruction. I.e., there is only one edge from the predecessor, and it's to
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// the loop header.
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MachineBasicBlock *MBB = Preds.front();
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// Now move the instructions to the predecessors.
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for (std::vector<MachineBasicBlock*>::iterator
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I = Preds.begin(), E = Preds.end(); I != E; ++I)
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MoveInstToBlock(*I, MI.clone());
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// FIXME: We are assuming at first that the basic blocks coming into this loop
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// have only one successor each. This isn't the case in general because we
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// haven't broken critical edges or added preheaders.
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if (MBB->succ_size() != 1) return;
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assert(*MBB->succ_begin() == CurLoop->getHeader() &&
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"The predecessor doesn't feed directly into the loop header!");
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// Now move the instructions to the predecessor.
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MoveInstToEndOfBlock(MBB, MI.clone());
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// Hoisting was successful! Remove bothersome instruction now.
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MI.getParent()->remove(&MI);
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Changed = true;
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return true;
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}
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