From 43750eab828f181294e14b9821e9152d75b2d1e6 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Fri, 3 Jun 2016 10:38:09 +0000 Subject: [PATCH] [mips] EABI CodeGen is completely untested and seems to have bitrotted. Remove it. Summary: There are no tests*, no EABI buildbots, and simple test cases do not work. * There is a single MIPS16 test using a mips*-gnueabi triple but this test doesn't test EABI and the triple doesn't cause EABI to be used. Reviewers: sdardis Subscribers: tberghammer, danalbert, srhines, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D20906 llvm-svn: 271658 --- .../Target/Mips/MCTargetDesc/MipsABIInfo.cpp | 4 +- .../Target/Mips/MCTargetDesc/MipsABIInfo.h | 4 +- llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 10 ---- llvm/lib/Target/Mips/MipsCallingConv.td | 48 ------------------- llvm/lib/Target/Mips/MipsISelLowering.cpp | 1 - llvm/lib/Target/Mips/MipsSubtarget.cpp | 3 +- llvm/lib/Target/Mips/MipsSubtarget.h | 2 - 7 files changed, 3 insertions(+), 69 deletions(-) diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp index 97b24ede0cd1..8164abf2238b 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp @@ -42,7 +42,7 @@ ArrayRef MipsABIInfo::GetVarArgRegs() const { unsigned MipsABIInfo::GetCalleeAllocdArgSizeInBytes(CallingConv::ID CC) const { if (IsO32()) return CC != CallingConv::Fast ? 16 : 0; - if (IsN32() || IsN64() || IsEABI()) + if (IsN32() || IsN64()) return 0; llvm_unreachable("Unhandled ABI"); } @@ -55,8 +55,6 @@ MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU, return MipsABIInfo::N32(); else if (Options.getABIName().startswith("n64")) return MipsABIInfo::N64(); - else if (Options.getABIName().startswith("eabi")) - return MipsABIInfo::EABI(); else if (!Options.getABIName().empty()) llvm_unreachable("Unknown ABI option for MIPS"); diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h index 06d1251e6d4d..4ea45e56702c 100644 --- a/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h +++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h @@ -23,7 +23,7 @@ class TargetRegisterClass; class MipsABIInfo { public: - enum class ABI { Unknown, O32, N32, N64, EABI }; + enum class ABI { Unknown, O32, N32, N64 }; protected: ABI ThisABI; @@ -35,7 +35,6 @@ public: static MipsABIInfo O32() { return MipsABIInfo(ABI::O32); } static MipsABIInfo N32() { return MipsABIInfo(ABI::N32); } static MipsABIInfo N64() { return MipsABIInfo(ABI::N64); } - static MipsABIInfo EABI() { return MipsABIInfo(ABI::EABI); } static MipsABIInfo computeTargetABI(const Triple &TT, StringRef CPU, const MCTargetOptions &Options); @@ -43,7 +42,6 @@ public: bool IsO32() const { return ThisABI == ABI::O32; } bool IsN32() const { return ThisABI == ABI::N32; } bool IsN64() const { return ThisABI == ABI::N64; } - bool IsEABI() const { return ThisABI == ABI::EABI; } ABI GetEnumValue() const { return ThisABI; } /// The registers to use for byval arguments. diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 2809f47e9fb6..e6333f9a4b76 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -313,7 +313,6 @@ const char *MipsAsmPrinter::getCurrentABIString() const { case MipsABIInfo::ABI::O32: return "abi32"; case MipsABIInfo::ABI::N32: return "abiN32"; case MipsABIInfo::ABI::N64: return "abi64"; - case MipsABIInfo::ABI::EABI: return "eabi32"; // TODO: handle eabi64 default: llvm_unreachable("Unknown Mips ABI"); } } @@ -713,15 +712,6 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { // TODO: handle O64 ABI - if (ABI.IsEABI()) { - if (STI.isGP32bit()) - OutStreamer->SwitchSection(OutContext.getELFSection(".gcc_compiled_long32", - ELF::SHT_PROGBITS, 0)); - else - OutStreamer->SwitchSection(OutContext.getELFSection(".gcc_compiled_long64", - ELF::SHT_PROGBITS, 0)); - } - TS.updateABIInfo(STI); // We should always emit a '.module fp=...' but binutils 2.24 does not accept diff --git a/llvm/lib/Target/Mips/MipsCallingConv.td b/llvm/lib/Target/Mips/MipsCallingConv.td index 0b4b7785af67..a57cb7badc17 100644 --- a/llvm/lib/Target/Mips/MipsCallingConv.td +++ b/llvm/lib/Target/Mips/MipsCallingConv.td @@ -211,48 +211,6 @@ def RetCC_MipsN : CallingConv<[ CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>> ]>; -//===----------------------------------------------------------------------===// -// Mips EABI Calling Convention -//===----------------------------------------------------------------------===// - -def CC_MipsEABI : CallingConv<[ - // Promote i8/i16 arguments to i32. - CCIfType<[i8, i16], CCPromoteToType>, - - // Integer arguments are passed in integer registers. - CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, - - // Single fp arguments are passed in pairs within 32-bit mode - CCIfType<[f32], CCIfSubtarget<"isSingleFloat()", - CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>, - - CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()", - CCAssignToReg<[F12, F14, F16, F18]>>>, - - // The first 4 double fp arguments are passed in single fp registers. - CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", - CCAssignToReg<[D6, D7, D8, D9]>>>, - - // Integer values get stored in stack slots that are 4 bytes in - // size and 4-byte aligned. - CCIfType<[i32, f32], CCAssignToStack<4, 4>>, - - // Integer values get stored in stack slots that are 8 bytes in - // size and 8-byte aligned. - CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>> -]>; - -def RetCC_MipsEABI : CallingConv<[ - // i32 are returned in registers V0, V1 - CCIfType<[i32], CCAssignToReg<[V0, V1]>>, - - // f32 are returned in registers F0, F1 - CCIfType<[f32], CCAssignToReg<[F0, F1]>>, - - // f64 are returned in register D0 - CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>> -]>; - //===----------------------------------------------------------------------===// // Mips FastCC Calling Convention //===----------------------------------------------------------------------===// @@ -325,7 +283,6 @@ def CC_Mips_FastCC : CallingConv<[ // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned. CCIfType<[i32, f32], CCAssignToStack<4, 4>>, - CCIfSubtarget<"isABI_EABI()", CCDelegateTo>, CCIfSubtarget<"isABI_O32()", CCDelegateTo>, CCDelegateTo ]>; @@ -335,7 +292,6 @@ def CC_Mips_FastCC : CallingConv<[ //===----------------------------------------------------------------------===// def RetCC_Mips : CallingConv<[ - CCIfSubtarget<"isABI_EABI()", CCDelegateTo>, CCIfSubtarget<"isABI_N32()", CCDelegateTo>, CCIfSubtarget<"isABI_N64()", CCDelegateTo>, CCDelegateTo @@ -377,8 +333,6 @@ def CC_Mips_FixedArg : CallingConv<[ CCIfCC<"CallingConv::Fast", CCDelegateTo>, - // FIXME: There wasn't an EABI case in the original code and it seems unlikely - // that it's the same as CC_MipsN CCIfSubtarget<"isABI_O32()", CCDelegateTo>, CCDelegateTo ]>; @@ -386,8 +340,6 @@ def CC_Mips_FixedArg : CallingConv<[ def CC_Mips_VarArg : CallingConv<[ CCIfByVal>, - // FIXME: There wasn't an EABI case in the original code and it seems unlikely - // that it's the same as CC_MipsN_VarArg CCIfSubtarget<"isABI_O32()", CCDelegateTo>, CCDelegateTo ]>; diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 64cb7db1eb42..239b372fc55a 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -2670,7 +2670,6 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, DAG.getCopyFromReg(Chain, DL, ABI.IsN64() ? Mips::SP_64 : Mips::SP, getPointerTy(DAG.getDataLayout())); - // With EABI is it possible to have 16 args on registers. std::deque< std::pair > RegsToPass; SmallVector MemOpChains; diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index 8a18b517d16b..20915379f966 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -90,7 +90,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, const std::string &CPU, report_fatal_error("Code generation for MIPS-V is not implemented", false); // Check if Architecture and ABI are compatible. - assert(((!isGP64bit() && (isABI_O32() || isABI_EABI())) || + assert(((!isGP64bit() && isABI_O32()) || (isGP64bit() && (isABI_N32() || isABI_N64()))) && "Invalid Arch & ABI pair."); @@ -164,7 +164,6 @@ Reloc::Model MipsSubtarget::getRelocationModel() const { return TM.getRelocationModel(); } -bool MipsSubtarget::isABI_EABI() const { return getABI().IsEABI(); } bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); } bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); } bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); } diff --git a/llvm/lib/Target/Mips/MipsSubtarget.h b/llvm/lib/Target/Mips/MipsSubtarget.h index ea020bb30170..287ca674c5b6 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.h +++ b/llvm/lib/Target/Mips/MipsSubtarget.h @@ -163,8 +163,6 @@ public: void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override; CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const override; - /// Only O32 and EABI supported right now. - bool isABI_EABI() const; bool isABI_N64() const; bool isABI_N32() const; bool isABI_O32() const;