forked from OSchip/llvm-project
[SystemZ] Simplify handling of 128-bit multiply/divide instruction
Several integer multiply/divide instructions require use of a register pair as input and output. This patch moves setting up the input register pair from C++ code to TableGen, simplifying the whole process and making it more easily extensible. No functional change. llvm-svn: 307155
This commit is contained in:
Ulrich Weigand
parent
e2a68e96f0
commit
43579cf4a0
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@ -2224,15 +2224,12 @@ static void lowerMUL_LOHI32(SelectionDAG &DAG, const SDLoc &DL, unsigned Extend,
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// Lower a binary operation that produces two VT results, one in each
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// half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
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// Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
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// on the extended Op0 and (unextended) Op1. Store the even register result
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// and Opcode performs the GR128 operation. Store the even register result
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// in Even and the odd register result in Odd.
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static void lowerGR128Binary(SelectionDAG &DAG, const SDLoc &DL, EVT VT,
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unsigned Extend, unsigned Opcode, SDValue Op0,
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SDValue Op1, SDValue &Even, SDValue &Odd) {
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SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
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SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
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SDValue(In128, 0), Op1);
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unsigned Opcode, SDValue Op0, SDValue Op1,
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SDValue &Even, SDValue &Odd) {
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SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped, Op0, Op1);
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bool Is32Bit = is32Bit(VT);
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Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
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Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
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@ -2962,7 +2959,7 @@ SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
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lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
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Op.getOperand(1), Ops[1], Ops[0]);
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else {
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// Do a full 128-bit multiplication based on UMUL_LOHI64:
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// Do a full 128-bit multiplication based on SystemZISD::UMUL_LOHI:
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//
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// (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
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//
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@ -2980,10 +2977,10 @@ SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
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SDValue RL = Op.getOperand(1);
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SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
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SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
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// UMUL_LOHI64 returns the low result in the odd register and the high
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// result in the even register. SMUL_LOHI is defined to return the
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// low half first, so the results are in reverse order.
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lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
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// SystemZISD::UMUL_LOHI returns the low result in the odd register and
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// the high result in the even register. ISD::SMUL_LOHI is defined to
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// return the low half first, so the results are in reverse order.
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lowerGR128Binary(DAG, DL, VT, SystemZISD::UMUL_LOHI,
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LL, RL, Ops[1], Ops[0]);
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SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
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SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
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@ -3004,10 +3001,10 @@ SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
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lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
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Op.getOperand(1), Ops[1], Ops[0]);
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else
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// UMUL_LOHI64 returns the low result in the odd register and the high
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// result in the even register. UMUL_LOHI is defined to return the
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// low half first, so the results are in reverse order.
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lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
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// SystemZISD::UMUL_LOHI returns the low result in the odd register and
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// the high result in the even register. ISD::UMUL_LOHI is defined to
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// return the low half first, so the results are in reverse order.
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lowerGR128Binary(DAG, DL, VT, SystemZISD::UMUL_LOHI,
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Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
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return DAG.getMergeValues(Ops, DL);
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}
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@ -3018,24 +3015,19 @@ SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
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SDValue Op1 = Op.getOperand(1);
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EVT VT = Op.getValueType();
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SDLoc DL(Op);
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unsigned Opcode;
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// We use DSGF for 32-bit division.
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if (is32Bit(VT)) {
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// We use DSGF for 32-bit division. This means the first operand must
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// always be 64-bit, and the second operand should be 32-bit whenever
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// that is possible, to improve performance.
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if (is32Bit(VT))
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Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
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Opcode = SystemZISD::SDIVREM32;
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} else if (DAG.ComputeNumSignBits(Op1) > 32) {
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else if (DAG.ComputeNumSignBits(Op1) > 32)
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Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
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Opcode = SystemZISD::SDIVREM32;
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} else
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Opcode = SystemZISD::SDIVREM64;
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// DSG(F) takes a 64-bit dividend, so the even register in the GR128
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// input is "don't care". The instruction returns the remainder in
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// the even register and the quotient in the odd register.
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// DSG(F) returns the remainder in the even register and the
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// quotient in the odd register.
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SDValue Ops[2];
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lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
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Op0, Op1, Ops[1], Ops[0]);
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lowerGR128Binary(DAG, DL, VT, SystemZISD::SDIVREM, Op0, Op1, Ops[1], Ops[0]);
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return DAG.getMergeValues(Ops, DL);
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}
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@ -3044,16 +3036,11 @@ SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
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EVT VT = Op.getValueType();
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SDLoc DL(Op);
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// DL(G) uses a double-width dividend, so we need to clear the even
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// register in the GR128 input. The instruction returns the remainder
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// in the even register and the quotient in the odd register.
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// DL(G) returns the remainder in the even register and the
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// quotient in the odd register.
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SDValue Ops[2];
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if (is32Bit(VT))
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lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
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Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
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else
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lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
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Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
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lowerGR128Binary(DAG, DL, VT, SystemZISD::UDIVREM,
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Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
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return DAG.getMergeValues(Ops, DL);
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}
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@ -4669,11 +4656,9 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
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OPCODE(SELECT_CCMASK);
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OPCODE(ADJDYNALLOC);
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OPCODE(POPCNT);
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OPCODE(UMUL_LOHI64);
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OPCODE(SDIVREM32);
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OPCODE(SDIVREM64);
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OPCODE(UDIVREM32);
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OPCODE(UDIVREM64);
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OPCODE(UMUL_LOHI);
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OPCODE(SDIVREM);
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OPCODE(UDIVREM);
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OPCODE(MVC);
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OPCODE(MVC_LOOP);
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OPCODE(NC);
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@ -5778,14 +5763,12 @@ SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI,
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return DoneMBB;
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}
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// Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
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// Emit an extension from a GR64 to a GR128. ClearEven is true
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// if the high register of the GR128 value must be cleared or false if
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// it's "don't care". SubReg is subreg_l32 when extending a GR32
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// and subreg_l64 when extending a GR64.
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// it's "don't care".
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MachineBasicBlock *SystemZTargetLowering::emitExt128(MachineInstr &MI,
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MachineBasicBlock *MBB,
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bool ClearEven,
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unsigned SubReg) const {
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bool ClearEven) const {
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MachineFunction &MF = *MBB->getParent();
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const SystemZInstrInfo *TII =
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static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
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@ -5808,7 +5791,7 @@ MachineBasicBlock *SystemZTargetLowering::emitExt128(MachineInstr &MI,
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In128 = NewIn128;
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}
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BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
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.addReg(In128).addReg(Src).addImm(SubReg);
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.addReg(In128).addReg(Src).addImm(SystemZ::subreg_l64);
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MI.eraseFromParent();
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return MBB;
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@ -6172,12 +6155,10 @@ MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
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case SystemZ::CondStoreF64Inv:
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return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
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case SystemZ::AEXT128_64:
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return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
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case SystemZ::ZEXT128_32:
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return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
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case SystemZ::ZEXT128_64:
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return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
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case SystemZ::AEXT128:
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return emitExt128(MI, MBB, false);
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case SystemZ::ZEXT128:
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return emitExt128(MI, MBB, true);
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case SystemZ::ATOMIC_SWAPW:
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return emitAtomicLoadBinary(MI, MBB, 0, 0);
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@ -86,14 +86,11 @@ enum NodeType : unsigned {
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// Count number of bits set in operand 0 per byte.
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POPCNT,
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// Wrappers around the ISD opcodes of the same name. The output and
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// first input operands are GR128s. The trailing numbers are the
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// widths of the second operand in bits.
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UMUL_LOHI64,
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SDIVREM32,
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SDIVREM64,
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UDIVREM32,
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UDIVREM64,
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// Wrappers around the ISD opcodes of the same name. The output is GR128.
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// Input operands may be GR64 or GR32, depending on the instruction.
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UMUL_LOHI,
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SDIVREM,
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UDIVREM,
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// Use a series of MVCs to copy bytes from one memory location to another.
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// The operands are:
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@ -562,7 +559,7 @@ private:
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unsigned StoreOpcode, unsigned STOCOpcode,
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bool Invert) const;
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MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
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bool ClearEven, unsigned SubReg) const;
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bool ClearEven) const;
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MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
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MachineBasicBlock *BB,
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unsigned BinOpcode, unsigned BitSize,
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@ -677,6 +677,22 @@ let Predicates = [FeatureLoadAndTrap] in {
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def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>;
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}
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// Extend GR64s to GR128s.
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let usesCustomInserter = 1 in
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def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
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//===----------------------------------------------------------------------===//
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// "Any" extensions
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//===----------------------------------------------------------------------===//
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// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
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def : Pat<(i64 (anyext GR32:$src)),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
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// Extend GR64s to GR128s.
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let usesCustomInserter = 1 in
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def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
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//===----------------------------------------------------------------------===//
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// Truncations
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//===----------------------------------------------------------------------===//
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@ -1216,13 +1232,17 @@ def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>;
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// Multiplication of a register, producing two results.
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def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>;
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def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>;
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def MLGR : BinaryRRE<"mlgr", 0xB986, z_umul_lohi64, GR128, GR64>;
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def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>;
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def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2),
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(MLGR (AEXT128 GR64:$src1), GR64:$src2)>;
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// Multiplication of memory, producing two results.
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def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>;
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def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>;
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def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>;
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def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
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def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>;
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def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))),
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(MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
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//===----------------------------------------------------------------------===//
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// Division and remainder
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@ -1230,19 +1250,38 @@ def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
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let hasSideEffects = 1 in { // Do not speculatively execute.
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// Division and remainder, from registers.
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def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>;
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def DSGFR : BinaryRRE<"dsgfr", 0xB91D, z_sdivrem32, GR128, GR32>;
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def DSGR : BinaryRRE<"dsgr", 0xB90D, z_sdivrem64, GR128, GR64>;
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def DLR : BinaryRRE<"dlr", 0xB997, z_udivrem32, GR128, GR32>;
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def DLGR : BinaryRRE<"dlgr", 0xB987, z_udivrem64, GR128, GR64>;
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def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>;
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def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>;
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def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>;
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def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>;
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def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>;
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// Division and remainder, from memory.
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def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>;
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def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
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def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>;
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def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>;
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def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
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def D : BinaryRX <"d", 0x5D, null_frag, GR128, load, 4>;
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def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, load, 4>;
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def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, load, 8>;
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def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, load, 4>;
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def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, load, 8>;
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}
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def : Pat<(z_sdivrem GR64:$src1, GR32:$src2),
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(DSGFR (AEXT128 GR64:$src1), GR32:$src2)>;
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def : Pat<(z_sdivrem GR64:$src1, (i32 (load bdxaddr20only:$src2))),
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(DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
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def : Pat<(z_sdivrem GR64:$src1, GR64:$src2),
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(DSGR (AEXT128 GR64:$src1), GR64:$src2)>;
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def : Pat<(z_sdivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))),
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(DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
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def : Pat<(z_udivrem GR32:$src1, GR32:$src2),
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(DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,
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subreg_l32)), GR32:$src2)>;
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def : Pat<(z_udivrem GR32:$src1, (i32 (load bdxaddr20only:$src2))),
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(DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,
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subreg_l32)), bdxaddr20only:$src2)>;
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def : Pat<(z_udivrem GR64:$src1, GR64:$src2),
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(DLGR (ZEXT128 GR64:$src1), GR64:$src2)>;
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def : Pat<(z_udivrem GR64:$src1, (i64 (load bdxaddr20only:$src2))),
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(DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>;
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//===----------------------------------------------------------------------===//
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// Shifts
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@ -1894,17 +1933,6 @@ def : Pat<(ctlz GR64:$src),
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let Predicates = [FeaturePopulationCount], Defs = [CC] in
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def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>;
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// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
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def : Pat<(i64 (anyext GR32:$src)),
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(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
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// Extend GR32s and GR64s to GR128s.
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let usesCustomInserter = 1 in {
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def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
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def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
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def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
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}
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// Search a block of memory for a character.
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let mayLoad = 1, Defs = [CC] in
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defm SRST : StringRRE<"srst", 0xB25E, z_search_string>;
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@ -36,14 +36,10 @@ def SDT_ZWrapOffset : SDTypeProfile<1, 2,
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SDTCisSameAs<0, 2>,
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SDTCisPtrTy<0>]>;
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def SDT_ZAdjDynAlloc : SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
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def SDT_ZGR128Binary32 : SDTypeProfile<1, 2,
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def SDT_ZGR128Binary : SDTypeProfile<1, 2,
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[SDTCisVT<0, untyped>,
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SDTCisVT<1, untyped>,
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SDTCisVT<2, i32>]>;
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def SDT_ZGR128Binary64 : SDTypeProfile<1, 2,
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[SDTCisVT<0, untyped>,
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SDTCisVT<1, untyped>,
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SDTCisVT<2, i64>]>;
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SDTCisInt<1>,
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SDTCisInt<2>]>;
|
||||
def SDT_ZAtomicLoadBinaryW : SDTypeProfile<1, 5,
|
||||
[SDTCisVT<0, i32>,
|
||||
SDTCisPtrTy<1>,
|
||||
|
|
@ -185,11 +181,9 @@ def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask,
|
|||
[SDNPInGlue]>;
|
||||
def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>;
|
||||
def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>;
|
||||
def z_umul_lohi64 : SDNode<"SystemZISD::UMUL_LOHI64", SDT_ZGR128Binary64>;
|
||||
def z_sdivrem32 : SDNode<"SystemZISD::SDIVREM32", SDT_ZGR128Binary32>;
|
||||
def z_sdivrem64 : SDNode<"SystemZISD::SDIVREM64", SDT_ZGR128Binary64>;
|
||||
def z_udivrem32 : SDNode<"SystemZISD::UDIVREM32", SDT_ZGR128Binary32>;
|
||||
def z_udivrem64 : SDNode<"SystemZISD::UDIVREM64", SDT_ZGR128Binary64>;
|
||||
def z_umul_lohi : SDNode<"SystemZISD::UMUL_LOHI", SDT_ZGR128Binary>;
|
||||
def z_sdivrem : SDNode<"SystemZISD::SDIVREM", SDT_ZGR128Binary>;
|
||||
def z_udivrem : SDNode<"SystemZISD::UDIVREM", SDT_ZGR128Binary>;
|
||||
|
||||
def z_membarrier : SDNode<"SystemZISD::MEMBARRIER", SDTNone,
|
||||
[SDNPHasChain, SDNPSideEffect]>;
|
||||
|
|
|
|||
|
|
@ -694,8 +694,8 @@ def : InstRW<[FXa, Lat6, GroupAlone], (instregex "FLOGR$")>;
|
|||
def : InstRW<[FXa, Lat3], (instregex "POPCNT$")>;
|
||||
|
||||
// Extend
|
||||
def : InstRW<[FXa], (instregex "AEXT128_64$")>;
|
||||
def : InstRW<[FXa], (instregex "ZEXT128_(32|64)$")>;
|
||||
def : InstRW<[FXa], (instregex "AEXT128$")>;
|
||||
def : InstRW<[FXa], (instregex "ZEXT128$")>;
|
||||
|
||||
// String instructions
|
||||
def : InstRW<[FXa, LSU, Lat30], (instregex "SRST$")>;
|
||||
|
|
|
|||
|
|
@ -627,8 +627,8 @@ def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
|
|||
def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
|
||||
|
||||
// Extend
|
||||
def : InstRW<[FXU], (instregex "AEXT128_64$")>;
|
||||
def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
|
||||
def : InstRW<[FXU], (instregex "AEXT128$")>;
|
||||
def : InstRW<[FXU], (instregex "ZEXT128$")>;
|
||||
|
||||
// String instructions
|
||||
def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
|
||||
|
|
|
|||
|
|
@ -665,8 +665,8 @@ def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>;
|
|||
def : InstRW<[FXU, Lat3], (instregex "POPCNT$")>;
|
||||
|
||||
// Extend
|
||||
def : InstRW<[FXU], (instregex "AEXT128_64$")>;
|
||||
def : InstRW<[FXU], (instregex "ZEXT128_(32|64)$")>;
|
||||
def : InstRW<[FXU], (instregex "AEXT128$")>;
|
||||
def : InstRW<[FXU], (instregex "ZEXT128$")>;
|
||||
|
||||
// String instructions
|
||||
def : InstRW<[FXU, LSU, Lat30], (instregex "SRST$")>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue