forked from OSchip/llvm-project
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng. I've done my best to consolidate the patches with those that were done by Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed anything. I've completely reorganized the thumb2 td file, made more extensive uses of multiclass, etc. Test cases will be contributed later after I re-organize what's in svn first. llvm-svn: 73965
This commit is contained in:
Evan Cheng
parent
cdf2b2dfea
commit
431cf567de
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@ -248,12 +248,122 @@ namespace ARM_AM {
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return V == 0;
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}
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/// getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed
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/// by a left shift. Returns the shift amount to use.
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static inline unsigned getThumbImm16ValShift(unsigned Imm) {
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// 16-bit (or less) immediates are trivially immediate operand with a shift
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// of zero.
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if ((Imm & ~65535U) == 0) return 0;
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// Use CTZ to compute the shift amount.
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return CountTrailingZeros_32(Imm);
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}
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/// isThumbImm16ShiftedVal - Return true if the specified value can be
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/// obtained by left shifting a 16-bit immediate.
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static inline bool isThumbImm16ShiftedVal(unsigned V) {
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// If this can be handled with
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V = (~65535U << getThumbImm16ValShift(V)) & V;
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return V == 0;
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}
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/// getThumbImmNonShiftedVal - If V is a value that satisfies
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/// isThumbImmShiftedVal, return the non-shiftd value.
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static inline unsigned getThumbImmNonShiftedVal(unsigned V) {
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return V >> getThumbImmValShift(V);
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}
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/// getT2SOImmValDecode - Given a 12-bit encoded Thumb-2 modified immediate,
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/// return the corresponding 32-bit immediate value.
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/// See ARM Reference Manual A6.3.2.
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static inline unsigned getT2SOImmValDecode(unsigned Imm) {
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unsigned Base = Imm & 0xff;
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switch ((Imm >> 8) & 0xf) {
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case 0:
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return Base;
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case 1:
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return Base | (Base << 16);
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case 2:
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return (Base << 8) | (Base << 24);
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case 3:
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return Base | (Base << 8) | (Base << 16) | (Base << 24);
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default:
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break;
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}
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// shifted immediate
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unsigned RotAmount = ((Imm >> 7) & 0x1f) - 8;
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return (Base | 0x80) << (24 - RotAmount);
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}
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/// getT2SOImmValSplat - Return the 12-bit encoded representation
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/// if the specified value can be obtained by splatting the low 8 bits
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/// into every other byte or every byte of a 32-bit value. i.e.,
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/// 00000000 00000000 00000000 abcdefgh control = 0
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/// 00000000 abcdefgh 00000000 abcdefgh control = 1
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/// abcdefgh 00000000 abcdefgh 00000000 control = 2
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/// abcdefgh abcdefgh abcdefgh abcdefgh control = 3
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/// Return -1 if none of the above apply.
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/// See ARM Reference Manual A6.3.2.
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static inline int getT2SOImmValSplat (unsigned V) {
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unsigned u, Vs, Imm;
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// control = 0
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if ((V & 0xffffff00) == 0)
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return V;
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// If the value is zeroes in the first byte, just shift those off
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Vs = ((V & 0xff) == 0) ? V >> 8 : V;
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// Any passing value only has 8 bits of payload, splatted across the word
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Imm = Vs & 0xff;
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// Likewise, any passing values have the payload splatted into the 3rd byte
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u = Imm | (Imm << 16);
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// control = 1 or 2
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if (Vs == u)
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return (((Vs == V) ? 1 : 2) << 8) | Imm;
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// control = 3
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if (Vs == (u | (u << 8)))
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return (3 << 8) | Imm;
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return -1;
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}
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/// getT2SOImmValRotate - Return the 12-bit encoded representation if the
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/// specified value is a rotated 8-bit value. Return -1 if no rotation
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/// encoding is possible.
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/// See ARM Reference Manual A6.3.2.
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static inline int getT2SOImmValRotate (unsigned V) {
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unsigned RotAmt = CountLeadingZeros_32(V);
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if (RotAmt >= 24)
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return -1;
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// If 'Arg' can be handled with a single shifter_op return the value.
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if ((rotr32(0xff000000U, RotAmt) & V) == V)
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return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
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return -1;
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}
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/// getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit
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/// into a Thumb-2 shifter_operand immediate operand, return the 12-bit
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/// encoding for it. If not, return -1.
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/// See ARM Reference Manual A6.3.2.
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static inline int getT2SOImmVal(unsigned Arg) {
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// If 'Arg' is an 8-bit splat, then get the encoded value.
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int Splat = getT2SOImmValSplat(Arg);
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if (Splat != -1)
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return Splat;
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// If 'Arg' can be handled with a single shifter_op return the value.
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int Rot = getT2SOImmValRotate(Arg);
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if (Rot != -1)
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return Rot;
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return -1;
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #2
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//===--------------------------------------------------------------------===//
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@ -751,6 +751,26 @@ class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb, HasV5T];
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}
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// T2I - Thumb2 instruction.
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class Thumb2I<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
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string asm, string cstr, list<dag> pattern>
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: InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
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let OutOperandList = outs;
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let InOperandList = ins;
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let AsmString = asm;
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let Pattern = pattern;
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list<Predicate> Predicates = [IsThumb, HasThumb2];
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}
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class T2I<dag outs, dag ins, string asm, list<dag> pattern>
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: Thumb2I<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
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// Thumb2Pat - Same as Pat<>, but requires that the compiler be in Thumb2 mode.
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class Thumb2Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb, HasThumb2];
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -98,6 +98,7 @@ def HasVFP2 : Predicate<"Subtarget->hasVFP2()">;
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def HasVFP3 : Predicate<"Subtarget->hasVFP3()">;
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def HasNEON : Predicate<"Subtarget->hasNEON()">;
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def IsThumb : Predicate<"Subtarget->isThumb()">;
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def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">;
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def HasThumb2 : Predicate<"Subtarget->hasThumb2()">;
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def IsARM : Predicate<"!Subtarget->isThumb()">;
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def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
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@ -20,131 +20,233 @@ def t2_so_reg : Operand<i32>, // reg imm
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let MIOperandInfo = (ops GPR, i32imm);
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}
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def LO16 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned short)N->getZExtValue());
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// t2_so_imm_XFORM - Return a t2_so_imm value packed into the format
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// described for t2_so_imm def below.
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def t2_so_imm_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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ARM_AM::getT2SOImmVal(N->getZExtValue()), MVT::i32);
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}]>;
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def HI16 : SDNodeXForm<imm, [{
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// Transformation function: shift the immediate value down into the low bits.
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return getI32Imm((unsigned)N->getZExtValue() >> 16);
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// t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
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def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())), MVT::i32);
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}]>;
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def imm16high : PatLeaf<(i32 imm), [{
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// Returns true if all bits out of the [31..16] range are 0.
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return ((N->getZExtValue() & 0xFFFF0000ULL) == N->getZExtValue());
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}], HI16>;
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// t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
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def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(
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ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())), MVT::i32);
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}]>;
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def imm16high0xffff : PatLeaf<(i32 imm), [{
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// Returns true if lo 16 bits are set and this is a 32-bit value.
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return ((N->getZExtValue() & 0x0000FFFFULL) == 0xFFFFULL);
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}], HI16>;
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// t2_so_imm - Match a 32-bit immediate operand, which is an
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// 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit
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// immediate splatted into multiple bytes of the word. t2_so_imm values are
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// represented in the imm field in the same 12-bit form that they are encoded
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// into t2_so_imm instructions: the 8-bit immediate is the least significant bits
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// [bits 0-7], the 4-bit shift/splat amount is the next 4 bits [bits 8-11].
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def t2_so_imm : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::getT2SOImmVal((uint32_t)N->getZExtValue()) != -1;
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}], t2_so_imm_XFORM> {
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let PrintMethod = "printT2SOImmOperand";
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}
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def imm0_4095 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 4096;
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}]>;
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// t2_so_imm_not - Match an immediate that is a complement
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// of a t2_so_imm.
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def t2_so_imm_not : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1;
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}], t2_so_imm_not_XFORM> {
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let PrintMethod = "printT2SOImmOperand";
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}
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// t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm.
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def t2_so_imm_neg : Operand<i32>,
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PatLeaf<(imm), [{
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return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
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}], t2_so_imm_neg_XFORM> {
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let PrintMethod = "printT2SOImmOperand";
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}
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/// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095].
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def imm0_4095 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 4096;
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}]>;
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def imm0_4095_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)-N->getZExtValue() < 4096;
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return (uint32_t)(-N->getZExtValue()) < 4096;
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}], imm_neg_XFORM>;
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def imm0_65535 : PatLeaf<(i32 imm), [{
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return N->getZExtValue() < 65536;
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}]>;
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// A6.3.2 Modified immediate constants in Thumb instructions (#<const>)
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// FIXME: Move it the the addrmode matcher code.
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def t2_so_imm : PatLeaf<(i32 imm), [{
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uint64_t v = N->getZExtValue();
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if (v == 0 || v > 0xffffffffUL) return false;
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// variant1 - 0b0000x - 8-bit which could be zero (not supported for now)
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// variant2 - 0b00nnx - 8-bit repeated inside the 32-bit room
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unsigned hi16 = (unsigned)(v >> 16);
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unsigned lo16 = (unsigned)(v & 0xffffUL);
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bool valid = (hi16 == lo16) && (
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(v & 0x00ff00ffUL) == 0 || // type 0001x
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(v & 0xff00ff00UL) == 0 || // type 0010x
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((lo16 >> 8) == (lo16 & 0xff))); // type 0011x
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if (valid) return true;
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// variant3 - 0b01000..0b11111 - 8-bit shifted inside the 32-bit room
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unsigned shift = CountLeadingZeros_32(v);
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uint64_t mask = (0xff000000ULL >> shift);
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// If valid, it is type 01000 + shift
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return ((shift < 24) && (v & mask) > 0) && ((v & (~mask)) == 0);
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/// imm0_65535 predicate - True if the 32-bit immediate is in the range
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/// [0.65535].
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def imm0_65535 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getZExtValue() < 65536;
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}]>;
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/// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield
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/// e.g., 0xf000ffff
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def bf_inv_mask_imm : Operand<i32>,
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PatLeaf<(imm), [{
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uint32_t v = (uint32_t)N->getZExtValue();
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if (v == 0xffffffff)
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return 0;
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// naive checker. should do better, but simple is best for now since it's
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// more likely to be correct.
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while (v & 1) v >>= 1; // shift off the leading 1's
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if (v)
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{
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while (!(v & 1)) v >>=1; // shift off the mask
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while (v & 1) v >>= 1; // shift off the trailing 1's
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}
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// if this is a mask for clearing a bitfield, what's left should be zero.
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return (v == 0);
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}] > {
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let PrintMethod = "printBitfieldInvMaskImmOperand";
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}
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/// Split a 32-bit immediate into two 16 bit parts.
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def t2_lo16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff,
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MVT::i32);
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}]>;
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def t2_hi16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32);
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}]>;
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def t2_lo16AllZero : PatLeaf<(i32 imm), [{
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// Returns true if all low 16-bits are 0.
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return (((uint32_t)N->getZExtValue()) & 0xFFFFUL) == 0;
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}], t2_hi16>;
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//===----------------------------------------------------------------------===//
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// Thumb-2 to cover the functionality of the ARM instruction set.
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// Thumb2 to cover the functionality of the ARM instruction set.
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//
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/// T2I_bin_irs - Defines a set of (op reg, {so_imm|reg|so_reg}) patterns for a
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/// T2I_bin_is - Defines a set of (op reg, {so_imm|so_reg}) patterns for a
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// binary operation that produces a value.
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multiclass T2I_bin_irs<string opc, PatFrag opnode> {
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multiclass T2I_bin_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[HasThumb2]>;
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// register
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def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[HasThumb2]>;
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def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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// shifted register
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def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
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Requires<[HasThumb2]>;
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def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
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}
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/// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
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/// T2I_2bin_is - Same as T2I_bin_is except the order of operands are reversed.
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multiclass T2I_rbin_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
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// shifted register
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def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
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!strconcat(opc, " $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
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}
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/// T2I_bin_s_is - Similar to T2I_bin_is except it sets the 's' bit so the
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/// instruction modifies the CPSR register.
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let Defs = [CPSR] in {
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multiclass T2I_bin_s_irs<string opc, PatFrag opnode> {
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multiclass T2I_bin_s_is<string opc, PatFrag opnode> {
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// shifted imm
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def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
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Requires<[HasThumb2]>;
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// register
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def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
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Requires<[HasThumb2]>;
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def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
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[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
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// shifted register
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def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
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!strconcat(opc, "s $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
|
||||
Requires<[HasThumb2]>;
|
||||
def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
|
||||
!strconcat(opc, "s $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
|
||||
}
|
||||
}
|
||||
|
||||
/// T2I_bin_c_irs - Similar to T2I_bin_irs except it uses the 's' bit. Also the
|
||||
/// instruction can optionally set the CPSR register.
|
||||
/// T2I_rbin_s_is - Same as T2I_bin_s_is except the order of operands are
|
||||
/// reversed.
|
||||
let Defs = [CPSR] in {
|
||||
multiclass T2I_rbin_s_is<string opc, PatFrag opnode> {
|
||||
// shifted imm
|
||||
def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs),
|
||||
!strconcat(opc, "s $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
|
||||
|
||||
// shifted register
|
||||
def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs),
|
||||
!strconcat(opc, "s $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
|
||||
}
|
||||
}
|
||||
|
||||
/// T2I_bin_ii12s - Defines a set of (op reg, {so_imm|imm0_4095|so_reg}) patterns
|
||||
/// for a binary operation that produces a value.
|
||||
multiclass T2I_bin_ii12s<string opc, PatFrag opnode> {
|
||||
// shifted imm
|
||||
def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs),
|
||||
!strconcat(opc, " $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
|
||||
// 12-bit imm
|
||||
def ri12 : T2I<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
|
||||
!strconcat(opc, "w $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode GPR:$lhs, imm0_4095:$rhs))]>;
|
||||
// shifted register
|
||||
def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
|
||||
!strconcat(opc, " $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
|
||||
}
|
||||
|
||||
/// T2I_bin_c_is - Defines a set of (op reg, {so_imm|reg}) patterns for a
|
||||
// binary operation that produces a value and set the carry bit. It can also
|
||||
/// optionally set CPSR.
|
||||
let Uses = [CPSR] in {
|
||||
multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
|
||||
multiclass T2I_bin_c_is<string opc, PatFrag opnode> {
|
||||
// shifted imm
|
||||
def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs, cc_out:$s),
|
||||
!strconcat(opc, "${s} $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
|
||||
Requires<[HasThumb2]>;
|
||||
|
||||
// register
|
||||
def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s),
|
||||
!strconcat(opc, "${s} $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
|
||||
Requires<[HasThumb2]>;
|
||||
def ri : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_imm:$rhs, cc_out:$s),
|
||||
!strconcat(opc, "${s} $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>;
|
||||
|
||||
// shifted register
|
||||
def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
|
||||
!strconcat(opc, "${s} $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
|
||||
Requires<[HasThumb2]>;
|
||||
def rs : T2I<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
|
||||
!strconcat(opc, "${s} $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>;
|
||||
}
|
||||
}
|
||||
|
||||
/// T2I_rbin_c_is - Same as T2I_bin_c_is except the order of operands are
|
||||
/// reversed.
|
||||
let Uses = [CPSR] in {
|
||||
multiclass T2I_rbin_c_is<string opc, PatFrag opnode> {
|
||||
// shifted imm
|
||||
def ri : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_imm:$lhs, cc_out:$s),
|
||||
!strconcat(opc, "${s} $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode t2_so_imm:$lhs, GPR:$rhs))]>;
|
||||
|
||||
// shifted register
|
||||
def rs : T2I<(outs GPR:$dst), (ins GPR:$rhs, t2_so_reg:$lhs, cc_out:$s),
|
||||
!strconcat(opc, "${s} $dst, $lhs, $rhs"),
|
||||
[(set GPR:$dst, (opnode t2_so_reg:$lhs, GPR:$rhs))]>;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/// T21_cmp_irs - Defines a set of (op r, {so_imm|so_reg}) cmp / test
|
||||
/// patterns. Similar to T2I_bin_is except the instruction does not produce
|
||||
/// a explicit result, only implicitly set CPSR.
|
||||
let Uses = [CPSR] in {
|
||||
multiclass T2I_cmp_is<string opc, PatFrag opnode> {
|
||||
// shifted imm
|
||||
def ri : T2I<(outs), (ins GPR:$lhs, t2_so_imm:$rhs),
|
||||
!strconcat(opc, " $lhs, $rhs"),
|
||||
[(opnode GPR:$lhs, t2_so_imm:$rhs)]>;
|
||||
|
||||
// shifted register
|
||||
def rs : T2I<(outs), (ins GPR:$lhs, t2_so_reg:$rhs),
|
||||
!strconcat(opc, " $lhs, $rhs"),
|
||||
[(opnode GPR:$lhs, t2_so_reg:$rhs)]>;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -155,54 +257,184 @@ multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
|
|||
//===----------------------------------------------------------------------===//
|
||||
// Move Instructions.
|
||||
//
|
||||
def tMOVi16 : PseudoInst<(outs GPR:$dst), (ins i32imm:$src),
|
||||
"movw $dst, $src",
|
||||
[(set GPR:$dst, imm0_65535:$src)]>,
|
||||
Requires<[HasThumb2]>;
|
||||
|
||||
let neverHasSideEffects = 1 in
|
||||
def t2MOVr : T2I<(outs GPR:$dst), (ins GPR:$src),
|
||||
"mov $dst, $src", []>;
|
||||
|
||||
def t2MOVi16 : T2I<(outs GPR:$dst), (ins i32imm:$src),
|
||||
"movw $dst, $src",
|
||||
[(set GPR:$dst, imm0_65535:$src)]>;
|
||||
|
||||
|
||||
// FIXME: Move (shifted register) is a pseudo-instruction for ASR, LSL, LSR,
|
||||
// ROR, and RRX. Consider splitting into multiple instructions.
|
||||
def t2MOVs : T2I<(outs GPR:$dst), (ins so_reg:$src),
|
||||
"mov $dst, $src",
|
||||
[(set GPR:$dst, so_reg:$src)]>;
|
||||
def t2MOVrx : T2I<(outs GPR:$dst), (ins GPR:$src),
|
||||
"mov $dst, $src, rrx",
|
||||
[(set GPR:$dst, (ARMrrx GPR:$src))]>;
|
||||
|
||||
|
||||
// FIXME: Also available in ARM mode.
|
||||
let Constraints = "$src = $dst" in
|
||||
def tMOVTi16 : PseudoInst<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
|
||||
"movt $dst, $imm",
|
||||
[(set GPR:$dst, (or (and GPR:$src, 0xffff),
|
||||
imm16high:$imm))]>,
|
||||
Requires<[HasThumb2]>;
|
||||
|
||||
def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff:$imm2),
|
||||
(tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>,
|
||||
Requires<[HasThumb2]>;
|
||||
|
||||
def : Pat<(i32 imm:$imm),
|
||||
(tMOVTi16 (tMOVi16 (LO16 imm:$imm)),(HI16 imm:$imm))>,
|
||||
Requires<[HasThumb2]>;
|
||||
def t2MOVTi16 : T2I<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
|
||||
"movt $dst, $imm",
|
||||
[(set GPR:$dst,
|
||||
(or (and GPR:$src, 0xffff), t2_lo16AllZero:$imm))]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Arithmetic Instructions.
|
||||
//
|
||||
defm t2ADD : T2I_bin_irs <"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
|
||||
defm t2SUB : T2I_bin_irs <"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
|
||||
|
||||
def tADDri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
|
||||
"add $dst, $lhs, $rhs",
|
||||
[(set GPR:$dst, (add GPR:$lhs, imm0_4095:$rhs))]>,
|
||||
Requires<[HasThumb2]>;
|
||||
def tSUBri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
|
||||
"sub $dst, $lhs, $rhs",
|
||||
[(set GPR:$dst, (add GPR:$lhs, imm0_4095_neg:$rhs))]>,
|
||||
Requires<[HasThumb2]>;
|
||||
defm t2ADD : T2I_bin_ii12s<"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
|
||||
defm t2SUB : T2I_bin_ii12s<"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
|
||||
|
||||
defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
|
||||
defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
||||
// ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants.
|
||||
defm t2ADDS : T2I_bin_s_is<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
|
||||
defm t2SUBS : T2I_bin_s_is<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
||||
|
||||
defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
|
||||
defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
|
||||
// FIXME: predication support
|
||||
defm t2ADC : T2I_bin_c_is<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
|
||||
defm t2SBC : T2I_bin_c_is<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
|
||||
|
||||
// RSB, RSC
|
||||
defm t2RSB : T2I_rbin_is <"rsb", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
|
||||
defm t2RSBS : T2I_rbin_c_is<"rsb", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
|
||||
defm t2RSC : T2I_rbin_s_is<"rsc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
|
||||
|
||||
// (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
|
||||
def : Thumb2Pat<(add GPR:$src, t2_so_imm_neg:$imm),
|
||||
(t2SUBri GPR:$src, t2_so_imm_neg:$imm)>;
|
||||
def : Thumb2Pat<(add GPR:$src, imm0_4095_neg:$imm),
|
||||
(t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>;
|
||||
|
||||
|
||||
def tMLS : PseudoInst<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
||||
"mls $dst, $a, $b, $c",
|
||||
[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
|
||||
Requires<[HasThumb2]>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Bitwise Instructions.
|
||||
//
|
||||
|
||||
def tORNrs : PseudoInst<(outs GPR:$dst), (ins GPR:$src1, t2_so_reg:$src2),
|
||||
"orn $dst, $src1, $src2",
|
||||
[(set GPR:$dst, (or GPR:$src1, (not t2_so_reg: $src2)))]>,
|
||||
Requires<[HasThumb2]>;
|
||||
defm t2AND : T2I_bin_is <"and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
|
||||
defm t2ORR : T2I_bin_is <"orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
|
||||
defm t2EOR : T2I_bin_is <"eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
|
||||
|
||||
defm t2BIC : T2I_bin_is <"bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
|
||||
|
||||
def : Thumb2Pat<(and GPR:$src, t2_so_imm_not:$imm),
|
||||
(t2BICri GPR:$src, t2_so_imm_not:$imm)>;
|
||||
|
||||
defm t2ORN : T2I_bin_is <"orn", BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
|
||||
|
||||
def : Thumb2Pat<(or GPR:$src, t2_so_imm_not:$imm),
|
||||
(t2ORNri GPR:$src, t2_so_imm_not:$imm)>;
|
||||
|
||||
|
||||
def t2MVNr : T2I<(outs GPR:$dst), (ins t2_so_reg:$rhs),
|
||||
"mvn $dst, $rhs",
|
||||
[(set GPR:$dst, (not t2_so_reg:$rhs))]>;
|
||||
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
|
||||
def t2MVNi : T2I<(outs GPR:$dst), (ins t2_so_imm_not:$rhs),
|
||||
"mvn $dst, $rhs",
|
||||
[(set GPR:$dst, t2_so_imm_not:$rhs)]>;
|
||||
|
||||
// A8.6.17 BFC - Bitfield clear
|
||||
// FIXME: Also available in ARM mode.
|
||||
let Constraints = "$src = $dst" in
|
||||
def t2BFC : T2I<(outs GPR:$dst), (ins GPR:$src, bf_inv_mask_imm:$imm),
|
||||
"bfc $dst, $imm",
|
||||
[(set GPR:$dst, (and GPR:$src, bf_inv_mask_imm:$imm))]>;
|
||||
|
||||
// FIXME: A8.6.18 BFI - Bitfield insert (Encoding T1)
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Multiply Instructions.
|
||||
//
|
||||
def t2MUL: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b),
|
||||
"mul $dst, $a, $b",
|
||||
[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
|
||||
|
||||
def t2MLA: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
||||
"mla $dst, $a, $b, $c",
|
||||
[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
|
||||
|
||||
def t2MLS: T2I<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
|
||||
"mls $dst, $a, $b, $c",
|
||||
[(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>;
|
||||
|
||||
// FIXME: SMULL, etc.
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Misc. Arithmetic Instructions.
|
||||
//
|
||||
|
||||
/////
|
||||
/// A8.6.31 CLZ
|
||||
/////
|
||||
// FIXME not firing? but ARM version does...
|
||||
def t2CLZ : T2I<(outs GPR:$dst), (ins GPR:$src),
|
||||
"clz $dst, $src",
|
||||
[(set GPR:$dst, (ctlz GPR:$src))]>;
|
||||
|
||||
def t2REV : T2I<(outs GPR:$dst), (ins GPR:$src),
|
||||
"rev $dst, $src",
|
||||
[(set GPR:$dst, (bswap GPR:$src))]>;
|
||||
|
||||
def t2REV16 : T2I<(outs GPR:$dst), (ins GPR:$src),
|
||||
"rev16 $dst, $src",
|
||||
[(set GPR:$dst,
|
||||
(or (and (srl GPR:$src, (i32 8)), 0xFF),
|
||||
(or (and (shl GPR:$src, (i32 8)), 0xFF00),
|
||||
(or (and (srl GPR:$src, (i32 8)), 0xFF0000),
|
||||
(and (shl GPR:$src, (i32 8)), 0xFF000000)))))]>;
|
||||
|
||||
/////
|
||||
/// A8.6.137 REVSH
|
||||
/////
|
||||
def t2REVSH : T2I<(outs GPR:$dst), (ins GPR:$src),
|
||||
"revsh $dst, $src",
|
||||
[(set GPR:$dst,
|
||||
(sext_inreg
|
||||
(or (srl (and GPR:$src, 0xFFFF), (i32 8)),
|
||||
(shl GPR:$src, (i32 8))), i16))]>;
|
||||
|
||||
// FIXME: PKHxx etc.
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Comparison Instructions...
|
||||
//
|
||||
|
||||
defm t2CMP : T2I_cmp_is<"cmp",
|
||||
BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>>;
|
||||
defm t2CMPnz : T2I_cmp_is<"cmp",
|
||||
BinOpFrag<(ARMcmpNZ node:$LHS, node:$RHS)>>;
|
||||
|
||||
defm t2CMN : T2I_cmp_is<"cmn",
|
||||
BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
|
||||
defm t2CMNnz : T2I_cmp_is<"cmn",
|
||||
BinOpFrag<(ARMcmpNZ node:$LHS,(ineg node:$RHS))>>;
|
||||
|
||||
def : Thumb2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm),
|
||||
(t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
|
||||
|
||||
def : Thumb2Pat<(ARMcmpNZ GPR:$src, t2_so_imm_neg:$imm),
|
||||
(t2CMNri GPR:$src, t2_so_imm_neg:$imm)>;
|
||||
|
||||
// FIXME: TST, TEQ, etc.
|
||||
|
||||
// A8.6.27 CBNZ, CBZ - Compare and branch on (non)zero.
|
||||
// Short range conditional branch. Looks awesome for loops. Need to figure
|
||||
// out how to use this one.
|
||||
|
||||
// FIXME: Conditional moves
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Non-Instruction Patterns
|
||||
//
|
||||
|
||||
// Large immediate handling.
|
||||
|
||||
def : Thumb2Pat<(i32 imm:$src),
|
||||
(t2MOVTi16 (t2MOVi16 (t2_lo16 imm:$src)),
|
||||
(t2_hi16 imm:$src))>;
|
||||
|
|
|
|||
|
|
@ -98,6 +98,7 @@ namespace {
|
|||
void printSOImm2PartOperand(const MachineInstr *MI, int opNum);
|
||||
void printSOOperand(const MachineInstr *MI, int OpNum);
|
||||
void printSORegOperand(const MachineInstr *MI, int opNum);
|
||||
void printT2SOImmOperand(const MachineInstr *MI, int opNum);
|
||||
void printAddrMode2Operand(const MachineInstr *MI, int OpNo);
|
||||
void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNo);
|
||||
void printAddrMode3Operand(const MachineInstr *MI, int OpNo);
|
||||
|
|
@ -108,6 +109,7 @@ namespace {
|
|||
const char *Modifier = 0);
|
||||
void printAddrModePCOperand(const MachineInstr *MI, int OpNo,
|
||||
const char *Modifier = 0);
|
||||
void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNo);
|
||||
void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNo);
|
||||
void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNo,
|
||||
unsigned Scale);
|
||||
|
|
@ -455,6 +457,24 @@ void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
|
|||
}
|
||||
}
|
||||
|
||||
static void printT2SOImm(raw_ostream &O, int64_t V) {
|
||||
unsigned Imm = ARM_AM::getT2SOImmValDecode(V);
|
||||
|
||||
// Always print the immediate directly, as the "rotate" form
|
||||
// is deprecated in some contexts.
|
||||
O << "#" << Imm;
|
||||
}
|
||||
|
||||
/// printT2SOImmOperand - T2SOImm is:
|
||||
/// 1. a 4-bit splat control value and 8 bit immediate value
|
||||
/// 2. a 5-bit rotate amount and a non-zero 8-bit immediate value
|
||||
/// represented by a normalizedin 7-bit value (msb is always 1)
|
||||
void ARMAsmPrinter::printT2SOImmOperand(const MachineInstr *MI, int OpNum) {
|
||||
const MachineOperand &MO = MI->getOperand(OpNum);
|
||||
assert(MO.isImm() && "Not a valid so_imm value!");
|
||||
printT2SOImm(O, MO.getImm());
|
||||
}
|
||||
|
||||
void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
|
||||
const MachineOperand &MO1 = MI->getOperand(Op);
|
||||
const MachineOperand &MO2 = MI->getOperand(Op+1);
|
||||
|
|
@ -619,6 +639,16 @@ void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
|
|||
O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
|
||||
}
|
||||
|
||||
void
|
||||
ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
|
||||
const MachineOperand &MO = MI->getOperand(Op);
|
||||
uint32_t v = ~MO.getImm();
|
||||
int32_t lsb = ffs (v) - 1;
|
||||
int32_t width = fls (v) - lsb;
|
||||
assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
|
||||
O << "#" << lsb << ", #" << width;
|
||||
}
|
||||
|
||||
void
|
||||
ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
|
||||
const MachineOperand &MO1 = MI->getOperand(Op);
|
||||
|
|
|
|||
Loading…
Reference in New Issue