forked from OSchip/llvm-project
Add support for NEON VLD3-dup instructions.
The encoding for alignment in VLD4-dup instructions is still a work in progress. llvm-svn: 120356
This commit is contained in:
Bob Wilson
parent
a994070040
commit
431ac4ef50
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@ -204,6 +204,13 @@ static const NEONLdStTableEntry NEONLdStTable[] = {
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{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 },
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{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 },
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{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, SingleSpc, 4, 4},
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{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, SingleSpc, 4, 4},
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{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, SingleSpc, 4, 2},
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{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, SingleSpc, 4, 2},
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{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, SingleSpc, 4, 8},
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{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, SingleSpc, 4, 8},
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{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 },
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{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 },
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{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 },
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@ -959,6 +966,12 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
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case ARM::VLD3DUPd8Pseudo_UPD:
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case ARM::VLD3DUPd16Pseudo_UPD:
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case ARM::VLD3DUPd32Pseudo_UPD:
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case ARM::VLD4DUPd8Pseudo:
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case ARM::VLD4DUPd16Pseudo:
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case ARM::VLD4DUPd32Pseudo:
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case ARM::VLD4DUPd8Pseudo_UPD:
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case ARM::VLD4DUPd16Pseudo_UPD:
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case ARM::VLD4DUPd32Pseudo_UPD:
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ExpandVLD(MBBI);
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break;
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@ -2367,6 +2367,12 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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return SelectVLDDup(N, 3, Opcodes);
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}
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case ARMISD::VLD4DUP: {
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unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
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ARM::VLD4DUPd32Pseudo };
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return SelectVLDDup(N, 4, Opcodes);
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}
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case ISD::INTRINSIC_VOID:
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case ISD::INTRINSIC_W_CHAIN: {
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unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
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@ -939,7 +939,59 @@ def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
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def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
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// VLD4DUP : Vector Load (single 4-element structure to all lanes)
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// FIXME: Not yet implemented.
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class VLD4DUP<bits<4> op7_4, string Dt>
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: NLdSt<1, 0b10, 0b1111, op7_4,
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(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
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(ins addrmode6:$Rn), IIC_VLD4dup,
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"vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
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let Rm = 0b1111;
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}
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def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8"> { let Inst{4} = Rn{4}; }
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def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16"> { let Inst{4} = Rn{4}; }
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def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> {
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let Inst{6} = Rn{5};
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let Inst{4} = Rn{5};
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}
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def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
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def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
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def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
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// ...with double-spaced registers (not used for codegen):
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def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8"> { let Inst{4} = Rn{4}; }
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def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16"> { let Inst{4} = Rn{4}; }
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def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> {
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let Inst{6} = Rn{5};
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let Inst{4} = Rn{5};
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}
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// ...with address register writeback:
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class VLD4DUPWB<bits<4> op7_4, string Dt>
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: NLdSt<1, 0b10, 0b1111, op7_4,
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(outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
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(ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4dupu,
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"vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
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"$Rn.addr = $wb", []>;
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def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8"> { let Inst{4} = Rn{4}; }
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def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16"> { let Inst{4} = Rn{4}; }
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def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> {
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let Inst{6} = Rn{5};
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let Inst{4} = Rn{5};
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}
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def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8"> { let Inst{4} = Rn{4}; }
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def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16"> { let Inst{4} = Rn{4}; }
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def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> {
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let Inst{6} = Rn{5};
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let Inst{4} = Rn{5};
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}
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def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
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def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
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def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
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} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
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let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
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@ -158,6 +158,8 @@ def IIC_VLD4 : InstrItinClass;
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def IIC_VLD4ln : InstrItinClass;
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def IIC_VLD4u : InstrItinClass;
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def IIC_VLD4lnu : InstrItinClass;
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def IIC_VLD4dup : InstrItinClass;
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def IIC_VLD4dupu : InstrItinClass;
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def IIC_VST1 : InstrItinClass;
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def IIC_VST1x2 : InstrItinClass;
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def IIC_VST1x3 : InstrItinClass;
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@ -595,6 +595,18 @@ def CortexA8Itineraries : ProcessorItineraries<
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InstrStage<5, [A8_LSPipe]>],
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[4, 4, 5, 5, 2, 1, 1, 1, 1, 1, 2, 2]>,
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//
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// VLD4dup
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InstrItinData<IIC_VLD4dup, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<3, [A8_NLSPipe], 0>,
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InstrStage<3, [A8_LSPipe]>],
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[2, 2, 3, 3, 1]>,
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//
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// VLD4dupu
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InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A8_Pipe0, A8_Pipe1]>,
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InstrStage<3, [A8_NLSPipe], 0>,
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InstrStage<3, [A8_LSPipe]>],
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[2, 2, 3, 3, 2, 1, 1]>,
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//
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// VST1
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InstrItinData<IIC_VST1, [InstrStage<1, [A8_Pipe0, A8_Pipe1], 0>,
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InstrStage<2, [A8_NLSPipe], 0>,
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@ -995,6 +995,24 @@ def CortexA9Itineraries : ProcessorItineraries<
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InstrStage<5, [A9_LSUnit]>],
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[5, 5, 6, 6, 2, 1, 1, 1, 1, 1, 2, 2]>,
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//
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// VLD4dup
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InstrItinData<IIC_VLD4dup, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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InstrStage<1, [A9_MUX0], 0>,
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InstrStage<1, [A9_DRegsN], 0, Required>,
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InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
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InstrStage<3, [A9_NPipe], 0>,
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InstrStage<3, [A9_LSUnit]>],
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[3, 3, 4, 4, 1]>,
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//
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// VLD4dupu
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InstrItinData<IIC_VLD4dupu, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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InstrStage<1, [A9_MUX0], 0>,
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InstrStage<1, [A9_DRegsN], 0, Required>,
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InstrStage<9, [A9_DRegsVFP], 0, Reserved>,
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InstrStage<3, [A9_NPipe], 0>,
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InstrStage<3, [A9_LSUnit]>],
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[3, 3, 4, 4, 2, 1, 1]>,
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//
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// VST1
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InstrItinData<IIC_VST1, [InstrStage<1, [A9_Issue0, A9_Issue1], 0>,
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InstrStage<1, [A9_MUX0], 0>,
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@ -91,3 +91,26 @@ define <4 x i16> @vld3dupi16(i16* %A) nounwind {
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}
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declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i16*, <4 x i16>, <4 x i16>, <4 x i16>, i32, i32) nounwind readonly
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%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
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define <2 x i32> @vld4dupi32(i32* %A) nounwind {
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;CHECK: vld4dupi32:
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;Check the alignment value. Max for this instruction is 128 bits:
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;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0, :128]
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%tmp0 = tail call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i32* %A, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, <2 x i32> undef, i32 0, i32 32)
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%tmp1 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 0
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%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
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%tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 1
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%tmp4 = shufflevector <2 x i32> %tmp3, <2 x i32> undef, <2 x i32> zeroinitializer
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%tmp5 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 2
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%tmp6 = shufflevector <2 x i32> %tmp5, <2 x i32> undef, <2 x i32> zeroinitializer
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%tmp7 = extractvalue %struct.__neon_int32x2x4_t %tmp0, 3
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%tmp8 = shufflevector <2 x i32> %tmp7, <2 x i32> undef, <2 x i32> zeroinitializer
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%tmp9 = add <2 x i32> %tmp2, %tmp4
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%tmp10 = add <2 x i32> %tmp6, %tmp8
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%tmp11 = add <2 x i32> %tmp9, %tmp10
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ret <2 x i32> %tmp11
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}
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declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i32*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32, i32) nounwind readonly
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