From 42f8ddeb115b8c575976254db43726dea06ca208 Mon Sep 17 00:00:00 2001
From: Dan Gohman <gohman@apple.com>
Date: Tue, 23 Mar 2010 22:15:31 +0000
Subject: [PATCH] Remove getTypeToExpandTo, since it isn't adding much value
 beyond just calling getTypeToTransformTo.

llvm-svn: 99335
---
 llvm/include/llvm/Target/TargetLowering.h     | 21 -------------------
 .../SelectionDAG/LegalizeIntegerTypes.cpp     |  5 +++--
 2 files changed, 3 insertions(+), 23 deletions(-)

diff --git a/llvm/include/llvm/Target/TargetLowering.h b/llvm/include/llvm/Target/TargetLowering.h
index da0f68606c6f..bb4168d399ed 100644
--- a/llvm/include/llvm/Target/TargetLowering.h
+++ b/llvm/include/llvm/Target/TargetLowering.h
@@ -268,27 +268,6 @@ public:
     return MVT(MVT::Other); // Not reached
   }
 
-  /// getTypeToExpandTo - For types supported by the target, this is an
-  /// identity function.  For types that must be expanded (i.e. integer types
-  /// that are larger than the largest integer register or illegal floating
-  /// point types), this returns the largest legal type it will be expanded to.
-  EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
-    assert(!VT.isVector());
-    while (true) {
-      switch (getTypeAction(Context, VT)) {
-      case Legal:
-        return VT;
-      case Expand:
-        VT = getTypeToTransformTo(Context, VT);
-        break;
-      default:
-        assert(false && "Type is not legal nor is it to be expanded!");
-        return VT;
-      }
-    }
-    return VT;
-  }
-
   /// getVectorTypeBreakdown - Vector types are broken down into some number of
   /// legal first class types.  For example, EVT::v8f32 maps to 2 EVT::v4f32
   /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 48f64c34d6d2..109281307d3a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1021,7 +1021,7 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
       Hi = InL;
     } else if (Amt == 1 &&
                TLI.isOperationLegalOrCustom(ISD::ADDC,
-                                            TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
+                                            TLI.getTypeToTransformTo(*DAG.getContext(), NVT))) {
       // Emit this X << 1 as X+X.
       SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
       SDValue LoOps[2] = { InL, InL };
@@ -1263,7 +1263,8 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
   bool hasCarry =
     TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
                                    ISD::ADDC : ISD::SUBC,
-                                 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
+                                 TLI.getTypeToTransformTo(*DAG.getContext(),
+                                                          NVT));
 
   if (hasCarry) {
     SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);