forked from OSchip/llvm-project
[AArch64] Remove overlapping scheduling definitions (NFC)
The scheduling definitions for ASIMD transpose and zipping overlapped with others a few lines below. Somehow, they didn't raise errors before. There seem to be other overlapping definitions. Somehow, they still don't raise errors. Differential revision: https://reviews.llvm.org/D68353
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@ -1517,25 +1517,6 @@ def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^MOVIv")>;
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// ASIMD move, FP immed
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// ASIMD move, FP immed
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def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMOVv")>;
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def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^FMOVv")>;
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// ASIMD table lookup, D-form
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def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8One")>;
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def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8Two")>;
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def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8Three")>;
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def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v8i8Four")>;
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// ASIMD table lookup, Q-form
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def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8One")>;
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def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8Two")>;
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def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8Three")>;
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def : InstRW<[THX2T99Write_7Cyc_F01], (instregex "^TB[LX]v16i8Four")>;
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// ASIMD transpose
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def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^TRN1", "^TRN2")>;
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// ASIMD unzip/zip
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def : InstRW<[THX2T99Write_5Cyc_F01],
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(instregex "^UZP1", "^UZP2", "^ZIP1", "^ZIP2")>;
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// ASIMD reciprocal estimate, D-form
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// ASIMD reciprocal estimate, D-form
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// ASIMD reciprocal estimate, Q-form
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// ASIMD reciprocal estimate, Q-form
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def : InstRW<[THX2T99Write_5Cyc_F01],
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def : InstRW<[THX2T99Write_5Cyc_F01],
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