forked from OSchip/llvm-project
LoopStrengthReduce: Try to pass address space to isLegalAddressingMode
This seems to only work some of the time. In some situations, this seems to use a nonsensical type and isn't actually aware of the memory being accessed. e.g. if branch condition is an icmp of a pointer, it checks the addressing mode of i1. llvm-svn: 245137
This commit is contained in:
Matt Arsenault
parent
3938f0c728
commit
427a0fd22e
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@ -105,6 +105,29 @@ static bool StressIVChain = false;
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namespace {
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struct MemAccessTy {
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/// Used in situations where the accessed memory type is unknown.
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static const unsigned UnknownAddressSpace = ~0u;
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Type *MemTy;
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unsigned AddrSpace;
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MemAccessTy() : MemTy(nullptr), AddrSpace(UnknownAddressSpace) {}
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MemAccessTy(Type *Ty, unsigned AS) :
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MemTy(Ty), AddrSpace(AS) {}
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bool operator==(MemAccessTy Other) const {
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return MemTy == Other.MemTy && AddrSpace == Other.AddrSpace;
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}
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bool operator!=(MemAccessTy Other) const { return !(*this == Other); }
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static MemAccessTy getUnknown(LLVMContext &Ctx) {
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return MemAccessTy(Type::getVoidTy(Ctx), UnknownAddressSpace);
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}
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};
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/// RegSortData - This class holds data which is used to order reuse candidates.
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class RegSortData {
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public:
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@ -683,11 +706,14 @@ static bool isAddressUse(Instruction *Inst, Value *OperandVal) {
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}
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/// getAccessType - Return the type of the memory being accessed.
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static Type *getAccessType(const Instruction *Inst) {
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Type *AccessTy = Inst->getType();
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if (const StoreInst *SI = dyn_cast<StoreInst>(Inst))
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AccessTy = SI->getOperand(0)->getType();
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else if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(Inst)) {
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static MemAccessTy getAccessType(const Instruction *Inst) {
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MemAccessTy AccessTy(Inst->getType(), MemAccessTy::UnknownAddressSpace);
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if (const StoreInst *SI = dyn_cast<StoreInst>(Inst)) {
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AccessTy.MemTy = SI->getOperand(0)->getType();
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AccessTy.AddrSpace = SI->getPointerAddressSpace();
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} else if (const LoadInst *LI = dyn_cast<LoadInst>(Inst)) {
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AccessTy.AddrSpace = LI->getPointerAddressSpace();
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} else if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(Inst)) {
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// Addressing modes can also be folded into prefetches and a variety
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// of intrinsics.
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switch (II->getIntrinsicID()) {
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@ -696,15 +722,15 @@ static Type *getAccessType(const Instruction *Inst) {
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case Intrinsic::x86_sse2_storeu_pd:
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case Intrinsic::x86_sse2_storeu_dq:
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case Intrinsic::x86_sse2_storel_dq:
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AccessTy = II->getArgOperand(0)->getType();
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AccessTy.MemTy = II->getArgOperand(0)->getType();
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break;
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}
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}
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// All pointers have the same requirements, so canonicalize them to an
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// arbitrary pointer type to minimize variation.
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if (PointerType *PTy = dyn_cast<PointerType>(AccessTy))
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AccessTy = PointerType::get(IntegerType::get(PTy->getContext(), 1),
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if (PointerType *PTy = dyn_cast<PointerType>(AccessTy.MemTy))
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AccessTy.MemTy = PointerType::get(IntegerType::get(PTy->getContext(), 1),
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PTy->getAddressSpace());
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return AccessTy;
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@ -1204,7 +1230,7 @@ public:
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typedef PointerIntPair<const SCEV *, 2, KindType> SCEVUseKindPair;
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KindType Kind;
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Type *AccessTy;
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MemAccessTy AccessTy;
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SmallVector<int64_t, 8> Offsets;
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int64_t MinOffset;
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@ -1236,11 +1262,9 @@ public:
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/// Regs - The set of register candidates used by all formulae in this LSRUse.
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SmallPtrSet<const SCEV *, 4> Regs;
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LSRUse(KindType K, Type *T) : Kind(K), AccessTy(T),
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MinOffset(INT64_MAX),
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MaxOffset(INT64_MIN),
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AllFixupsOutsideLoop(true),
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RigidFormula(false),
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LSRUse(KindType K, MemAccessTy AT)
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: Kind(K), AccessTy(AT), MinOffset(INT64_MAX), MaxOffset(INT64_MIN),
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AllFixupsOutsideLoop(true), RigidFormula(false),
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WidestFixupType(nullptr) {}
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bool HasFormulaWithSameRegs(const Formula &F) const;
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@ -1331,10 +1355,13 @@ void LSRUse::print(raw_ostream &OS) const {
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case ICmpZero: OS << "ICmpZero"; break;
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case Address:
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OS << "Address of ";
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if (AccessTy->isPointerTy())
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if (AccessTy.MemTy->isPointerTy())
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OS << "pointer"; // the full pointer type could be really verbose
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else
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OS << *AccessTy;
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else {
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OS << *AccessTy.MemTy;
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}
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OS << " in addrspace(" << AccessTy.AddrSpace << ')';
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}
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OS << ", Offsets={";
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@ -1360,12 +1387,13 @@ void LSRUse::dump() const {
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#endif
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static bool isAMCompletelyFolded(const TargetTransformInfo &TTI,
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LSRUse::KindType Kind, Type *AccessTy,
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LSRUse::KindType Kind, MemAccessTy AccessTy,
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GlobalValue *BaseGV, int64_t BaseOffset,
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bool HasBaseReg, int64_t Scale) {
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switch (Kind) {
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case LSRUse::Address:
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return TTI.isLegalAddressingMode(AccessTy, BaseGV, BaseOffset, HasBaseReg, Scale);
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return TTI.isLegalAddressingMode(AccessTy.MemTy, BaseGV, BaseOffset,
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HasBaseReg, Scale, AccessTy.AddrSpace);
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case LSRUse::ICmpZero:
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// There's not even a target hook for querying whether it would be legal to
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@ -1412,7 +1440,7 @@ static bool isAMCompletelyFolded(const TargetTransformInfo &TTI,
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static bool isAMCompletelyFolded(const TargetTransformInfo &TTI,
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int64_t MinOffset, int64_t MaxOffset,
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LSRUse::KindType Kind, Type *AccessTy,
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LSRUse::KindType Kind, MemAccessTy AccessTy,
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GlobalValue *BaseGV, int64_t BaseOffset,
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bool HasBaseReg, int64_t Scale) {
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// Check for overflow.
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@ -1433,7 +1461,7 @@ static bool isAMCompletelyFolded(const TargetTransformInfo &TTI,
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static bool isAMCompletelyFolded(const TargetTransformInfo &TTI,
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int64_t MinOffset, int64_t MaxOffset,
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LSRUse::KindType Kind, Type *AccessTy,
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LSRUse::KindType Kind, MemAccessTy AccessTy,
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const Formula &F) {
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// For the purpose of isAMCompletelyFolded either having a canonical formula
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// or a scale not equal to zero is correct.
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@ -1449,9 +1477,9 @@ static bool isAMCompletelyFolded(const TargetTransformInfo &TTI,
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/// isLegalUse - Test whether we know how to expand the current formula.
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static bool isLegalUse(const TargetTransformInfo &TTI, int64_t MinOffset,
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int64_t MaxOffset, LSRUse::KindType Kind, Type *AccessTy,
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GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg,
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int64_t Scale) {
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int64_t MaxOffset, LSRUse::KindType Kind,
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MemAccessTy AccessTy, GlobalValue *BaseGV,
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int64_t BaseOffset, bool HasBaseReg, int64_t Scale) {
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// We know how to expand completely foldable formulae.
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return isAMCompletelyFolded(TTI, MinOffset, MaxOffset, Kind, AccessTy, BaseGV,
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BaseOffset, HasBaseReg, Scale) ||
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@ -1463,8 +1491,8 @@ static bool isLegalUse(const TargetTransformInfo &TTI, int64_t MinOffset,
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}
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static bool isLegalUse(const TargetTransformInfo &TTI, int64_t MinOffset,
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int64_t MaxOffset, LSRUse::KindType Kind, Type *AccessTy,
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const Formula &F) {
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int64_t MaxOffset, LSRUse::KindType Kind,
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MemAccessTy AccessTy, const Formula &F) {
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return isLegalUse(TTI, MinOffset, MaxOffset, Kind, AccessTy, F.BaseGV,
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F.BaseOffset, F.HasBaseReg, F.Scale);
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}
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@ -1490,14 +1518,12 @@ static unsigned getScalingFactorCost(const TargetTransformInfo &TTI,
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switch (LU.Kind) {
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case LSRUse::Address: {
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// Check the scaling factor cost with both the min and max offsets.
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int ScaleCostMinOffset =
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TTI.getScalingFactorCost(LU.AccessTy, F.BaseGV,
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F.BaseOffset + LU.MinOffset,
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F.HasBaseReg, F.Scale);
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int ScaleCostMaxOffset =
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TTI.getScalingFactorCost(LU.AccessTy, F.BaseGV,
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F.BaseOffset + LU.MaxOffset,
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F.HasBaseReg, F.Scale);
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int ScaleCostMinOffset = TTI.getScalingFactorCost(
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LU.AccessTy.MemTy, F.BaseGV, F.BaseOffset + LU.MinOffset, F.HasBaseReg,
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F.Scale, LU.AccessTy.AddrSpace);
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int ScaleCostMaxOffset = TTI.getScalingFactorCost(
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LU.AccessTy.MemTy, F.BaseGV, F.BaseOffset + LU.MaxOffset, F.HasBaseReg,
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F.Scale, LU.AccessTy.AddrSpace);
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assert(ScaleCostMinOffset >= 0 && ScaleCostMaxOffset >= 0 &&
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"Legal addressing mode has an illegal cost!");
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@ -1515,7 +1541,7 @@ static unsigned getScalingFactorCost(const TargetTransformInfo &TTI,
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}
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static bool isAlwaysFoldable(const TargetTransformInfo &TTI,
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LSRUse::KindType Kind, Type *AccessTy,
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LSRUse::KindType Kind, MemAccessTy AccessTy,
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GlobalValue *BaseGV, int64_t BaseOffset,
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bool HasBaseReg) {
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// Fast-path: zero is always foldable.
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@ -1539,7 +1565,8 @@ static bool isAlwaysFoldable(const TargetTransformInfo &TTI,
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static bool isAlwaysFoldable(const TargetTransformInfo &TTI,
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ScalarEvolution &SE, int64_t MinOffset,
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int64_t MaxOffset, LSRUse::KindType Kind,
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Type *AccessTy, const SCEV *S, bool HasBaseReg) {
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MemAccessTy AccessTy, const SCEV *S,
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bool HasBaseReg) {
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// Fast-path: zero is always foldable.
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if (S->isZero()) return true;
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@ -1696,11 +1723,10 @@ class LSRInstance {
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UseMapTy UseMap;
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bool reconcileNewOffset(LSRUse &LU, int64_t NewOffset, bool HasBaseReg,
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LSRUse::KindType Kind, Type *AccessTy);
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LSRUse::KindType Kind, MemAccessTy AccessTy);
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std::pair<size_t, int64_t> getUse(const SCEV *&Expr,
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LSRUse::KindType Kind,
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Type *AccessTy);
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std::pair<size_t, int64_t> getUse(const SCEV *&Expr, LSRUse::KindType Kind,
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MemAccessTy AccessTy);
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void DeleteUse(LSRUse &LU, size_t LUIdx);
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@ -2152,16 +2178,18 @@ LSRInstance::OptimizeLoopTermCond() {
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C->getValue().isMinSignedValue())
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goto decline_post_inc;
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// Check for possible scaled-address reuse.
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Type *AccessTy = getAccessType(UI->getUser());
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MemAccessTy AccessTy = getAccessType(UI->getUser());
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int64_t Scale = C->getSExtValue();
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if (TTI.isLegalAddressingMode(AccessTy, /*BaseGV=*/ nullptr,
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/*BaseOffset=*/ 0,
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/*HasBaseReg=*/ false, Scale))
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if (TTI.isLegalAddressingMode(AccessTy.MemTy, /*BaseGV=*/nullptr,
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/*BaseOffset=*/0,
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/*HasBaseReg=*/false, Scale,
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AccessTy.AddrSpace))
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goto decline_post_inc;
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Scale = -Scale;
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if (TTI.isLegalAddressingMode(AccessTy, /*BaseGV=*/ nullptr,
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/*BaseOffset=*/ 0,
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/*HasBaseReg=*/ false, Scale))
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if (TTI.isLegalAddressingMode(AccessTy.MemTy, /*BaseGV=*/nullptr,
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/*BaseOffset=*/0,
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/*HasBaseReg=*/false, Scale,
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AccessTy.AddrSpace))
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goto decline_post_inc;
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}
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}
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@ -2216,12 +2244,12 @@ LSRInstance::OptimizeLoopTermCond() {
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/// reconcileNewOffset - Determine if the given use can accommodate a fixup
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/// at the given offset and other details. If so, update the use and
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/// return true.
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bool
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LSRInstance::reconcileNewOffset(LSRUse &LU, int64_t NewOffset, bool HasBaseReg,
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LSRUse::KindType Kind, Type *AccessTy) {
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bool LSRInstance::reconcileNewOffset(LSRUse &LU, int64_t NewOffset,
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bool HasBaseReg, LSRUse::KindType Kind,
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MemAccessTy AccessTy) {
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int64_t NewMinOffset = LU.MinOffset;
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int64_t NewMaxOffset = LU.MaxOffset;
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Type *NewAccessTy = AccessTy;
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MemAccessTy NewAccessTy = AccessTy;
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// Check for a mismatched kind. It's tempting to collapse mismatched kinds to
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// something conservative, however this can pessimize in the case that one of
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@ -2232,8 +2260,10 @@ LSRInstance::reconcileNewOffset(LSRUse &LU, int64_t NewOffset, bool HasBaseReg,
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// Check for a mismatched access type, and fall back conservatively as needed.
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// TODO: Be less conservative when the type is similar and can use the same
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// addressing modes.
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if (Kind == LSRUse::Address && AccessTy != LU.AccessTy)
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NewAccessTy = Type::getVoidTy(AccessTy->getContext());
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if (Kind == LSRUse::Address) {
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if (AccessTy != LU.AccessTy)
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NewAccessTy = MemAccessTy::getUnknown(AccessTy.MemTy->getContext());
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}
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// Conservatively assume HasBaseReg is true for now.
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if (NewOffset < LU.MinOffset) {
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@ -2260,9 +2290,9 @@ LSRInstance::reconcileNewOffset(LSRUse &LU, int64_t NewOffset, bool HasBaseReg,
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/// getUse - Return an LSRUse index and an offset value for a fixup which
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/// needs the given expression, with the given kind and optional access type.
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/// Either reuse an existing use or create a new one, as needed.
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std::pair<size_t, int64_t>
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LSRInstance::getUse(const SCEV *&Expr,
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LSRUse::KindType Kind, Type *AccessTy) {
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std::pair<size_t, int64_t> LSRInstance::getUse(const SCEV *&Expr,
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LSRUse::KindType Kind,
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MemAccessTy AccessTy) {
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const SCEV *Copy = Expr;
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int64_t Offset = ExtractImmediate(Expr, SE);
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@ -2831,10 +2861,10 @@ static bool canFoldIVIncExpr(const SCEV *IncExpr, Instruction *UserInst,
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if (IncConst->getValue()->getValue().getMinSignedBits() > 64)
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return false;
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MemAccessTy AccessTy = getAccessType(UserInst);
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int64_t IncOffset = IncConst->getValue()->getSExtValue();
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if (!isAlwaysFoldable(TTI, LSRUse::Address,
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getAccessType(UserInst), /*BaseGV=*/ nullptr,
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IncOffset, /*HaseBaseReg=*/ false))
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if (!isAlwaysFoldable(TTI, LSRUse::Address, AccessTy, /*BaseGV=*/nullptr,
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IncOffset, /*HaseBaseReg=*/false))
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return false;
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return true;
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@ -2961,7 +2991,7 @@ void LSRInstance::CollectFixupsAndInitialFormulae() {
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LF.PostIncLoops = U.getPostIncLoops();
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LSRUse::KindType Kind = LSRUse::Basic;
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Type *AccessTy = nullptr;
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MemAccessTy AccessTy;
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if (isAddressUse(LF.UserInst, LF.OperandValToReplace)) {
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Kind = LSRUse::Address;
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AccessTy = getAccessType(LF.UserInst);
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@ -3148,7 +3178,8 @@ LSRInstance::CollectLoopInvariantFixupsAndFormulae() {
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LSRFixup &LF = getNewFixup();
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LF.UserInst = const_cast<Instruction *>(UserInst);
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LF.OperandValToReplace = U;
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std::pair<size_t, int64_t> P = getUse(S, LSRUse::Basic, nullptr);
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std::pair<size_t, int64_t> P = getUse(
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S, LSRUse::Basic, MemAccessTy());
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LF.LUIdx = P.first;
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LF.Offset = P.second;
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LSRUse &LU = Uses[LF.LUIdx];
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@ -0,0 +1,156 @@
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=bonaire -loop-reduce < %s | FileCheck -check-prefix=OPT %s
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; Test that loops with different maximum offsets for different address
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; spaces are correctly handled.
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target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
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; OPT-LABEL: @test_global_addressing_loop_uniform_index_max_offset_i32(
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; OPT: {{^}}.lr.ph:
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; OPT: %lsr.iv2 = phi i8 addrspace(1)* [ %scevgep3, %.lr.ph ], [ %arg1, %.lr.ph.preheader ]
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; OPT: %scevgep4 = getelementptr i8, i8 addrspace(1)* %lsr.iv2, i64 4095
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; OPT: load i8, i8 addrspace(1)* %scevgep4, align 1
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define void @test_global_addressing_loop_uniform_index_max_offset_i32(i32 addrspace(1)* noalias nocapture %arg0, i8 addrspace(1)* noalias nocapture readonly %arg1, i32 %n) #0 {
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bb:
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%tmp = icmp sgt i32 %n, 0
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br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge
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.lr.ph.preheader: ; preds = %bb
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br label %.lr.ph
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._crit_edge.loopexit: ; preds = %.lr.ph
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br label %._crit_edge
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._crit_edge: ; preds = %._crit_edge.loopexit, %bb
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ret void
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.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
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%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]
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%tmp1 = add nuw nsw i64 %indvars.iv, 4095
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%tmp2 = getelementptr inbounds i8, i8 addrspace(1)* %arg1, i64 %tmp1
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%tmp3 = load i8, i8 addrspace(1)* %tmp2, align 1
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%tmp4 = sext i8 %tmp3 to i32
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%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i64 %indvars.iv
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%tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4
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%tmp7 = add nsw i32 %tmp6, %tmp4
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store i32 %tmp7, i32 addrspace(1)* %tmp5, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%lftr.wideiv = trunc i64 %indvars.iv.next to i32
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%exitcond = icmp eq i32 %lftr.wideiv, %n
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br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph
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}
|
||||
|
||||
; OPT-LABEL: @test_global_addressing_loop_uniform_index_max_offset_p1_i32(
|
||||
; OPT: {{^}}.lr.ph.preheader:
|
||||
; OPT: %scevgep2 = getelementptr i8, i8 addrspace(1)* %arg1, i64 4096
|
||||
; OPT: br label %.lr.ph
|
||||
|
||||
; OPT: {{^}}.lr.ph:
|
||||
; OPT: %lsr.iv3 = phi i8 addrspace(1)* [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]
|
||||
; OPT: %scevgep4 = getelementptr i8, i8 addrspace(1)* %lsr.iv3, i64 1
|
||||
define void @test_global_addressing_loop_uniform_index_max_offset_p1_i32(i32 addrspace(1)* noalias nocapture %arg0, i8 addrspace(1)* noalias nocapture readonly %arg1, i32 %n) #0 {
|
||||
bb:
|
||||
%tmp = icmp sgt i32 %n, 0
|
||||
br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge
|
||||
|
||||
.lr.ph.preheader: ; preds = %bb
|
||||
br label %.lr.ph
|
||||
|
||||
._crit_edge.loopexit: ; preds = %.lr.ph
|
||||
br label %._crit_edge
|
||||
|
||||
._crit_edge: ; preds = %._crit_edge.loopexit, %bb
|
||||
ret void
|
||||
|
||||
.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
|
||||
%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]
|
||||
%tmp1 = add nuw nsw i64 %indvars.iv, 4096
|
||||
%tmp2 = getelementptr inbounds i8, i8 addrspace(1)* %arg1, i64 %tmp1
|
||||
%tmp3 = load i8, i8 addrspace(1)* %tmp2, align 1
|
||||
%tmp4 = sext i8 %tmp3 to i32
|
||||
%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i64 %indvars.iv
|
||||
%tmp6 = load i32, i32 addrspace(1)* %tmp5, align 4
|
||||
%tmp7 = add nsw i32 %tmp6, %tmp4
|
||||
store i32 %tmp7, i32 addrspace(1)* %tmp5, align 4
|
||||
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
|
||||
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
|
||||
%exitcond = icmp eq i32 %lftr.wideiv, %n
|
||||
br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph
|
||||
}
|
||||
|
||||
; OPT-LABEL: @test_local_addressing_loop_uniform_index_max_offset_i32(
|
||||
; OPT: {{^}}.lr.ph
|
||||
; OPT: %lsr.iv2 = phi i8 addrspace(3)* [ %scevgep3, %.lr.ph ], [ %arg1, %.lr.ph.preheader ]
|
||||
; OPT: %scevgep4 = getelementptr i8, i8 addrspace(3)* %lsr.iv2, i32 65535
|
||||
; OPT: %tmp4 = load i8, i8 addrspace(3)* %scevgep4, align 1
|
||||
define void @test_local_addressing_loop_uniform_index_max_offset_i32(i32 addrspace(1)* noalias nocapture %arg0, i8 addrspace(3)* noalias nocapture readonly %arg1, i32 %n) #0 {
|
||||
bb:
|
||||
%tmp = icmp sgt i32 %n, 0
|
||||
br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge
|
||||
|
||||
.lr.ph.preheader: ; preds = %bb
|
||||
br label %.lr.ph
|
||||
|
||||
._crit_edge.loopexit: ; preds = %.lr.ph
|
||||
br label %._crit_edge
|
||||
|
||||
._crit_edge: ; preds = %._crit_edge.loopexit, %bb
|
||||
ret void
|
||||
|
||||
.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
|
||||
%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]
|
||||
%tmp1 = add nuw nsw i64 %indvars.iv, 65535
|
||||
%tmp2 = trunc i64 %tmp1 to i32
|
||||
%tmp3 = getelementptr inbounds i8, i8 addrspace(3)* %arg1, i32 %tmp2
|
||||
%tmp4 = load i8, i8 addrspace(3)* %tmp3, align 1
|
||||
%tmp5 = sext i8 %tmp4 to i32
|
||||
%tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i64 %indvars.iv
|
||||
%tmp7 = load i32, i32 addrspace(1)* %tmp6, align 4
|
||||
%tmp8 = add nsw i32 %tmp7, %tmp5
|
||||
store i32 %tmp8, i32 addrspace(1)* %tmp6, align 4
|
||||
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
|
||||
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
|
||||
%exitcond = icmp eq i32 %lftr.wideiv, %n
|
||||
br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph
|
||||
}
|
||||
|
||||
; OPT-LABEL: @test_local_addressing_loop_uniform_index_max_offset_p1_i32(
|
||||
; OPT: {{^}}.lr.ph.preheader:
|
||||
; OPT: %scevgep2 = getelementptr i8, i8 addrspace(3)* %arg1, i32 65536
|
||||
; OPT: br label %.lr.ph
|
||||
|
||||
; OPT: {{^}}.lr.ph:
|
||||
; OPT: %lsr.iv3 = phi i8 addrspace(3)* [ %scevgep4, %.lr.ph ], [ %scevgep2, %.lr.ph.preheader ]
|
||||
; OPT: %scevgep4 = getelementptr i8, i8 addrspace(3)* %lsr.iv3, i32 1
|
||||
define void @test_local_addressing_loop_uniform_index_max_offset_p1_i32(i32 addrspace(1)* noalias nocapture %arg0, i8 addrspace(3)* noalias nocapture readonly %arg1, i32 %n) #0 {
|
||||
bb:
|
||||
%tmp = icmp sgt i32 %n, 0
|
||||
br i1 %tmp, label %.lr.ph.preheader, label %._crit_edge
|
||||
|
||||
.lr.ph.preheader: ; preds = %bb
|
||||
br label %.lr.ph
|
||||
|
||||
._crit_edge.loopexit: ; preds = %.lr.ph
|
||||
br label %._crit_edge
|
||||
|
||||
._crit_edge: ; preds = %._crit_edge.loopexit, %bb
|
||||
ret void
|
||||
|
||||
.lr.ph: ; preds = %.lr.ph, %.lr.ph.preheader
|
||||
%indvars.iv = phi i64 [ %indvars.iv.next, %.lr.ph ], [ 0, %.lr.ph.preheader ]
|
||||
%tmp1 = add nuw nsw i64 %indvars.iv, 65536
|
||||
%tmp2 = trunc i64 %tmp1 to i32
|
||||
%tmp3 = getelementptr inbounds i8, i8 addrspace(3)* %arg1, i32 %tmp2
|
||||
%tmp4 = load i8, i8 addrspace(3)* %tmp3, align 1
|
||||
%tmp5 = sext i8 %tmp4 to i32
|
||||
%tmp6 = getelementptr inbounds i32, i32 addrspace(1)* %arg0, i64 %indvars.iv
|
||||
%tmp7 = load i32, i32 addrspace(1)* %tmp6, align 4
|
||||
%tmp8 = add nsw i32 %tmp7, %tmp5
|
||||
store i32 %tmp8, i32 addrspace(1)* %tmp6, align 4
|
||||
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
|
||||
%lftr.wideiv = trunc i64 %indvars.iv.next to i32
|
||||
%exitcond = icmp eq i32 %lftr.wideiv, %n
|
||||
br i1 %exitcond, label %._crit_edge.loopexit, label %.lr.ph
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hawaii" "unsafe-fp-math"="false" "use-soft-float"="false" }
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
if not 'AMDGPU' in config.root.targets:
|
||||
config.unsupported = True
|
||||
|
||||
|
|
@ -0,0 +1,113 @@
|
|||
; RUN: llc -march=amdgcn -mcpu=bonaire -print-lsr-output < %s 2>&1 | FileCheck %s
|
||||
|
||||
; Test various conditions where OptimizeLoopTermCond doesn't look at a
|
||||
; memory instruction use and fails to find the address space.
|
||||
|
||||
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
|
||||
|
||||
; CHECK-LABEL: @local_cmp_user(
|
||||
; CHECK: bb11:
|
||||
; CHECK: %lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb ], [ -2, %entry ]
|
||||
; CHECK: %lsr.iv = phi i32 [ %lsr.iv.next, %bb ], [ undef, %entry ]
|
||||
|
||||
; CHECK: bb:
|
||||
; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
|
||||
; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, 2
|
||||
; CHECK: %scevgep = getelementptr i8, i8 addrspace(3)* %t, i32 %lsr.iv.next2
|
||||
; CHECK: %c1 = icmp ult i8 addrspace(3)* %scevgep, undef
|
||||
define void @local_cmp_user() nounwind {
|
||||
entry:
|
||||
br label %bb11
|
||||
|
||||
bb11:
|
||||
%i = phi i32 [ 0, %entry ], [ %i.next, %bb ]
|
||||
%ii = shl i32 %i, 1
|
||||
%c0 = icmp eq i32 %i, undef
|
||||
br i1 %c0, label %bb13, label %bb
|
||||
|
||||
bb:
|
||||
%t = load i8 addrspace(3)*, i8 addrspace(3)* addrspace(3)* undef
|
||||
%p = getelementptr i8, i8 addrspace(3)* %t, i32 %ii
|
||||
%c1 = icmp ult i8 addrspace(3)* %p, undef
|
||||
%i.next = add i32 %i, 1
|
||||
br i1 %c1, label %bb11, label %bb13
|
||||
|
||||
bb13:
|
||||
unreachable
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @global_cmp_user(
|
||||
; CHECK: %lsr.iv.next = add i64 %lsr.iv, -1
|
||||
; CHECK: %lsr.iv.next2 = add i64 %lsr.iv1, 2
|
||||
; CHECK: %scevgep = getelementptr i8, i8 addrspace(1)* %t, i64 %lsr.iv.next2
|
||||
define void @global_cmp_user() nounwind {
|
||||
entry:
|
||||
br label %bb11
|
||||
|
||||
bb11:
|
||||
%i = phi i64 [ 0, %entry ], [ %i.next, %bb ]
|
||||
%ii = shl i64 %i, 1
|
||||
%c0 = icmp eq i64 %i, undef
|
||||
br i1 %c0, label %bb13, label %bb
|
||||
|
||||
bb:
|
||||
%t = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef
|
||||
%p = getelementptr i8, i8 addrspace(1)* %t, i64 %ii
|
||||
%c1 = icmp ult i8 addrspace(1)* %p, undef
|
||||
%i.next = add i64 %i, 1
|
||||
br i1 %c1, label %bb11, label %bb13
|
||||
|
||||
bb13:
|
||||
unreachable
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @global_gep_user(
|
||||
; CHECK: %p = getelementptr i8, i8 addrspace(1)* %t, i32 %lsr.iv1
|
||||
; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
|
||||
; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, 2
|
||||
define void @global_gep_user() nounwind {
|
||||
entry:
|
||||
br label %bb11
|
||||
|
||||
bb11:
|
||||
%i = phi i32 [ 0, %entry ], [ %i.next, %bb ]
|
||||
%ii = shl i32 %i, 1
|
||||
%c0 = icmp eq i32 %i, undef
|
||||
br i1 %c0, label %bb13, label %bb
|
||||
|
||||
bb:
|
||||
%t = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef
|
||||
%p = getelementptr i8, i8 addrspace(1)* %t, i32 %ii
|
||||
%c1 = icmp ult i8 addrspace(1)* %p, undef
|
||||
%i.next = add i32 %i, 1
|
||||
br i1 %c1, label %bb11, label %bb13
|
||||
|
||||
bb13:
|
||||
unreachable
|
||||
}
|
||||
|
||||
; CHECK-LABEL: @global_sext_scale_user(
|
||||
; CHECK: %p = getelementptr i8, i8 addrspace(1)* %t, i64 %ii.ext
|
||||
; CHECK: %lsr.iv.next = add i32 %lsr.iv, -1
|
||||
; CHECK: %lsr.iv.next2 = add i32 %lsr.iv1, 2
|
||||
define void @global_sext_scale_user() nounwind {
|
||||
entry:
|
||||
br label %bb11
|
||||
|
||||
bb11:
|
||||
%i = phi i32 [ 0, %entry ], [ %i.next, %bb ]
|
||||
%ii = shl i32 %i, 1
|
||||
%ii.ext = sext i32 %ii to i64
|
||||
%c0 = icmp eq i32 %i, undef
|
||||
br i1 %c0, label %bb13, label %bb
|
||||
|
||||
bb:
|
||||
%t = load i8 addrspace(1)*, i8 addrspace(1)* addrspace(1)* undef
|
||||
%p = getelementptr i8, i8 addrspace(1)* %t, i64 %ii.ext
|
||||
%c1 = icmp ult i8 addrspace(1)* %p, undef
|
||||
%i.next = add i32 %i, 1
|
||||
br i1 %c1, label %bb11, label %bb13
|
||||
|
||||
bb13:
|
||||
unreachable
|
||||
}
|
||||
Loading…
Reference in New Issue