forked from OSchip/llvm-project
AMDGPU/SI: Make comments more precise.
True branch instructions do behave as expected with liveness. Avoid the phrasing "branch decision is based on a value in an SGPR" because this could be misleading. A VALU compare instruction's result is still based on an SGPR, even though that condition may be divergent. llvm-svn: 245131
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@ -7,9 +7,8 @@
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// SALU instructions ignore control flow, so we need to modify the live ranges
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/// of the registers they define in some cases.
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/// \file SALU instructions ignore the execution mask, so we need to modify the
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/// live ranges of the registers they define in some cases.
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///
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/// The main case we need to handle is when a def is used in one side of a
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/// branch and not another. For example:
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@ -138,7 +137,8 @@ bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) {
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if (MBB.succ_size() < 2)
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continue;
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// We have structured control flow, so number of successors should be two.
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// We have structured control flow, so the number of successors should be
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// two.
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assert(MBB.succ_size() == 2);
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MachineBasicBlock *SuccA = *MBB.succ_begin();
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MachineBasicBlock *SuccB = *(++MBB.succ_begin());
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@ -161,10 +161,10 @@ bool SIFixSGPRLiveRanges::runOnMachineFunction(MachineFunction &MF) {
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unsigned Reg = RegLR.first;
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LiveRange *LR = RegLR.second;
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// FIXME: We could be smarter here. If the register is Live-In to
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// one block, but the other doesn't have any SGPR defs, then there
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// won't be a conflict. Also, if the branch decision is based on
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// a value in an SGPR, then there will be no conflict.
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// FIXME: We could be smarter here. If the register is Live-In to one
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// block, but the other doesn't have any SGPR defs, then there won't be a
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// conflict. Also, if the branch condition is uniform then there will be
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// no conflict.
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bool LiveInToA = LIS->isLiveInToMBB(*LR, SuccA);
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bool LiveInToB = LIS->isLiveInToMBB(*LR, SuccB);
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