forked from OSchip/llvm-project
[llvm] Call *set::insert without checking membership first (NFC)
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eca86cb2ed
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@ -831,8 +831,6 @@ public:
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void getBasicBlocks(DenseSet<BasicBlock *> &BBSet) const {
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for (IRInstructionData &ID : *this) {
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BasicBlock *BB = ID.Inst->getParent();
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if (BBSet.contains(BB))
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continue;
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BBSet.insert(BB);
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}
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}
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@ -843,9 +841,7 @@ public:
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SmallVector<BasicBlock *> &BBList) const {
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for (IRInstructionData &ID : *this) {
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BasicBlock *BB = ID.Inst->getParent();
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if (BBSet.contains(BB))
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continue;
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BBSet.insert(BB);
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if (BBSet.insert(BB).second)
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BBList.push_back(BB);
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}
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}
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@ -6020,31 +6020,25 @@ bool CodeGenPrepare::optimizePhiType(
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for (Value *V : Phi->incoming_values()) {
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if (auto *OpPhi = dyn_cast<PHINode>(V)) {
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if (!PhiNodes.count(OpPhi)) {
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if (Visited.count(OpPhi))
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if (!Visited.insert(OpPhi).second)
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return false;
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PhiNodes.insert(OpPhi);
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Visited.insert(OpPhi);
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Worklist.push_back(OpPhi);
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}
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} else if (auto *OpLoad = dyn_cast<LoadInst>(V)) {
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if (!OpLoad->isSimple())
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return false;
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if (!Defs.count(OpLoad)) {
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Defs.insert(OpLoad);
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if (Defs.insert(OpLoad).second)
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Worklist.push_back(OpLoad);
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}
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} else if (auto *OpEx = dyn_cast<ExtractElementInst>(V)) {
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if (!Defs.count(OpEx)) {
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Defs.insert(OpEx);
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if (Defs.insert(OpEx).second)
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Worklist.push_back(OpEx);
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}
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} else if (auto *OpBC = dyn_cast<BitCastInst>(V)) {
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if (!ConvertTy)
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ConvertTy = OpBC->getOperand(0)->getType();
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if (OpBC->getOperand(0)->getType() != ConvertTy)
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return false;
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if (!Defs.count(OpBC)) {
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Defs.insert(OpBC);
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if (Defs.insert(OpBC).second) {
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Worklist.push_back(OpBC);
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AnyAnchored |= !isa<LoadInst>(OpBC->getOperand(0)) &&
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!isa<ExtractElementInst>(OpBC->getOperand(0));
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@ -1298,7 +1298,6 @@ bool SwingSchedulerDAG::Circuits::circuit(int V, int S, NodeSetType &NodeSets,
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for (auto W : AdjK[V]) {
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if (W < S)
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continue;
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if (B[W].count(SV) == 0)
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B[W].insert(SV);
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}
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}
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@ -528,10 +528,8 @@ static void handleNormalInst(const MachineInstr &MI, LOHInfo *LOHInfos) {
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// count as MultiUser or block optimization. This is especially important on
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// arm64_32, where any memory operation is likely to be an explicit use of
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// xN and an implicit use of wN (the base address register).
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if (!UsesSeen.count(Idx)) {
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if (UsesSeen.insert(Idx).second)
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handleUse(MI, MO, LOHInfos[Idx]);
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UsesSeen.insert(Idx);
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}
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}
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}
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@ -3464,8 +3464,7 @@ AMDGPUAsmParser::validateConstantBusLimitations(const MCInst &Inst,
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// flat_scratch_lo, flat_scratch_hi
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// are theoretically valid but they are disabled anyway.
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// Note that this code mimics SIInstrInfo::verifyInstruction
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if (!SGPRsUsed.count(LastSGPR)) {
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SGPRsUsed.insert(LastSGPR);
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if (SGPRsUsed.insert(LastSGPR).second) {
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++ConstantBusUseCount;
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}
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} else { // Expression or a literal
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@ -349,8 +349,7 @@ void SIWholeQuadMode::markDefs(const MachineInstr &UseMI, LiveRange &LR,
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const VNInfo *NextValue = nullptr;
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const VisitKey Key(Value, DefinedLanes);
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if (!Visited.count(Key)) {
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Visited.insert(Key);
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if (Visited.insert(Key).second) {
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// On first visit to a phi then start processing first predecessor
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NextPredIdx = 0;
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}
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@ -192,10 +192,8 @@ private:
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void push_back(Value *V) {
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// Do not push back duplicates.
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if (!S.count(V)) {
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if (S.insert(V).second)
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Q.push_back(V);
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S.insert(V);
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}
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}
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Value *pop_front_val() {
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@ -222,10 +222,8 @@ private:
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assert(!Enterers.count(MBB));
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if (Blocks.insert(MBB).second) {
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for (auto *Pred : MBB->predecessors()) {
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if (!AddedToWorkList.count(Pred)) {
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if (AddedToWorkList.insert(Pred).second)
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WorkList.push_back(Pred);
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AddedToWorkList.insert(Pred);
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}
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}
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}
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}
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