forked from OSchip/llvm-project
[mlir][Linalg] NFC: Verify tiling on linalg.generic operation on tensors.
With the recent changes to linalg on tensor semantics, the tiling operations works out-of-the-box for generic operations. Add a test to verify that and some minor refactoring. Differential Revision: https://reviews.llvm.org/D93077
This commit is contained in:
MaheshRavishankar
parent
774c9c6ef3
commit
42444d0cf0
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@ -327,6 +327,21 @@ AffineMap inversePermutation(AffineMap map);
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/// ```
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AffineMap concatAffineMaps(ArrayRef<AffineMap> maps);
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/// Returns the map that results from projecting out the dimensions specified in
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/// `projectedDimensions`. The projected dimensions are set to 0.
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///
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/// Example:
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/// 1) map : affine_map<(d0, d1, d2) -> (d0, d1)>
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/// projected_dimensions : {2}
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/// result : affine_map<(d0, d1) -> (d0, d1)>
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///
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/// 2) map : affine_map<(d0, d1) -> (d0 + d1)>
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/// projected_dimensions : {1}
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/// result : affine_map<(d0) -> (d0)>
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///
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/// 3) map : affine_map<(d0, d1, d2) -> (d0, d1)>
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/// projected_dimensions : {1}
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/// result : affine_map<(d0, d1) -> (d0, 0)>
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AffineMap getProjectedMap(AffineMap map,
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ArrayRef<unsigned> projectedDimensions);
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@ -221,9 +221,8 @@ static bool isTiled(AffineMap map, ValueRange tileSizes) {
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static SmallVector<Value, 4>
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makeTiledShapes(OpBuilder &b, Location loc, LinalgOp linalgOp,
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ValueRange operands, AffineMap map, ValueRange ivs,
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ArrayRef<Value> tiledOperands, AffineMap map, ValueRange ivs,
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ValueRange tileSizes, ValueRange allShapeSizes) {
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assert(operands.size() == linalgOp.getShapedOperands().size());
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assert(ivs.size() == static_cast<size_t>(llvm::count_if(
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llvm::make_range(tileSizes.begin(), tileSizes.end()),
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[](Value v) { return !isZero(v); })) &&
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@ -243,11 +242,9 @@ makeTiledShapes(OpBuilder &b, Location loc, LinalgOp linalgOp,
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subShapeSizes.push_back(size - std_constant_index(1));
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}
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auto *op = linalgOp.getOperation();
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SmallVector<Value, 4> res;
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res.reserve(op->getNumOperands());
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for (auto en : llvm::enumerate(operands)) {
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res.reserve(tiledOperands.size());
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for (auto en : llvm::enumerate(tiledOperands)) {
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Value shapedOp = en.value();
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ShapedType shapedType = shapedOp.getType().cast<ShapedType>();
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unsigned rank = shapedType.getRank();
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@ -342,6 +339,7 @@ tileLinalgOpImpl(OpBuilder &b, LinalgOp op, ValueRange tileSizes,
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LoopIndexToRangeIndexMap loopIndexToRangeIndex;
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std::tie(loopRanges, loopIndexToRangeIndex) = makeTiledLoopRanges(
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b, op.getLoc(), shapeSizesToLoopsMap, allShapeSizes, tileSizes);
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SmallVector<Attribute, 4> iteratorTypes;
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for (auto attr :
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enumerate(op.iterator_types().cast<ArrayAttr>().getValue())) {
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@ -574,10 +572,10 @@ void mlir::linalg::populateLinalgTilingCanonicalizationPatterns(
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static void insertTilingPatterns(OwningRewritePatternList &patterns,
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const LinalgTilingOptions &options,
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MLIRContext *ctx) {
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RewritePatternList<
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RewritePatternList<GenericOp, IndexedGenericOp,
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#define GET_OP_LIST
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#include "mlir/Dialect/Linalg/IR/LinalgStructuredOps.cpp.inc"
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>::insert(patterns, options, ctx);
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>::insert(patterns, options, ctx);
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}
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static void applyTilingToLoopPatterns(LinalgTilingLoopType loopType,
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@ -1,4 +1,4 @@
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// RUN: mlir-opt %s -linalg-tile="linalg-tile-sizes=2,3,4" | FileCheck %s
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// RUN: mlir-opt %s -linalg-tile="linalg-tile-sizes=2,3,4" -split-input-file | FileCheck %s
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// CHECK-LABEL: func @matmul_tensors(
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// CHECK-SAME: %[[TA:[0-9a-z]+]]: tensor<?x?xf32>
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@ -26,3 +26,97 @@ func @matmul_tensors(
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// CHECK: return %[[TD0]] : tensor<?x?xf32>
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return %0 : tensor<?x?xf32>
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}
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// -----
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func @generic_op_tensors(
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%arg0 : tensor<?x?x?xf32>, %arg1 : tensor<?x?x?xf32>) -> tensor<?x?x?xf32> {
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%c0 = constant 0 : index
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%c1 = constant 1 : index
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%c2 = constant 2 : index
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%0 = dim %arg0, %c0 : tensor<?x?x?xf32>
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%1 = dim %arg0, %c1 : tensor<?x?x?xf32>
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%2 = dim %arg0, %c2 : tensor<?x?x?xf32>
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%3 = linalg.init_tensor [%0, %1, %2] : tensor<?x?x?xf32>
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%4 = linalg.generic
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{indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d1, d2)>,
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affine_map<(d0, d1, d2) -> (d0, d2, d1)>,
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affine_map<(d0, d1, d2) -> (d2, d1, d0)>],
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iterator_types = ["parallel", "parallel", "parallel"]}
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ins(%arg0, %arg1 : tensor<?x?x?xf32>, tensor<?x?x?xf32>)
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outs(%3 : tensor<?x?x?xf32>) {
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^bb0(%arg2 : f32, %arg3: f32, %arg4: f32):
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%5 = addf %arg2, %arg3 : f32
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linalg.yield %5 : f32
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} -> tensor<?x?x?xf32>
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return %4 : tensor<?x?x?xf32>
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}
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// CHECK-LABEL: func @generic_op_tensors
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// CHECK-SAME: %[[ARG0:[a-zA-Z0-9_]+]]: tensor<?x?x?xf32>
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// CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: tensor<?x?x?xf32>
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// CHECK: %[[INIT:.+]] = linalg.init_tensor
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// CHECK: %[[TD0:.+]] = scf.for %{{.+}} to %{{.+}} step %{{.+}} iter_args(%[[TC0:.+]] = %[[INIT]]) -> (tensor<?x?x?xf32>) {
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// CHECK: %[[TD1:.+]] = scf.for %{{.+}} to %{{.+}} step %{{.+}} iter_args(%[[TC1:.+]] = %[[TC0]]) -> (tensor<?x?x?xf32>) {
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// CHECK: %[[TD2:.+]] = scf.for %{{.+}} to %{{.+}} step %{{.+}} iter_args(%[[TC2:.+]] = %[[TC1]]) -> (tensor<?x?x?xf32>) {
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// CHECK: %[[STARG0:.+]] = subtensor %[[ARG0]][{{.+}}] : tensor<?x?x?xf32> to tensor<?x?x?xf32>
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// CHECK: %[[STARG1:.+]] = subtensor %[[ARG1]][{{.+}}] : tensor<?x?x?xf32> to tensor<?x?x?xf32>
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// CHECK: %[[STARG2:.+]] = subtensor %[[TC2]][{{.+}}] : tensor<?x?x?xf32> to tensor<?x?x?xf32>
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// CHECK: %[[STRETURN:.+]] = linalg.generic
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// CHECK-SAME: ins(%[[STARG0]], %[[STARG1]] : tensor<?x?x?xf32>, tensor<?x?x?xf32>)
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// CHECK-SAME: outs(%[[STARG2]] : tensor<?x?x?xf32>)
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// CHECK: %[[TD:.+]] = subtensor_insert %[[STRETURN]] into %[[TC2]]
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// CHECK: scf.yield %[[TD]]
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// CHECK: }
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// CHECK: scf.yield %[[TD2]]
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// CHECK: }
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// CHECK: scf.yield %[[TD1]]
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// CHECK: }
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// CHECK: return %[[TD0]]
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// -----
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func @indexed_generic_op_tensors(
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%arg0 : tensor<?x?x?xf32>, %arg1 : tensor<?x?x?xf32>) -> tensor<?x?x?xf32> {
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%c0 = constant 0 : index
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%c1 = constant 1 : index
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%c2 = constant 2 : index
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%0 = dim %arg0, %c0 : tensor<?x?x?xf32>
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%1 = dim %arg0, %c1 : tensor<?x?x?xf32>
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%2 = dim %arg0, %c2 : tensor<?x?x?xf32>
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%3 = linalg.init_tensor [%0, %1, %2] : tensor<?x?x?xf32>
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%4 = linalg.indexed_generic
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{indexing_maps = [affine_map<(d0, d1, d2) -> (d0, d1, d2)>,
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affine_map<(d0, d1, d2) -> (d0, d2, d1)>,
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affine_map<(d0, d1, d2) -> (d2, d1, d0)>],
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iterator_types = ["parallel", "parallel", "parallel"]}
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ins(%arg0, %arg1 : tensor<?x?x?xf32>, tensor<?x?x?xf32>)
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outs(%3 : tensor<?x?x?xf32>) {
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^bb0(%arg2 : index, %arg3 : index, %arg4 : index, %arg5 : f32, %arg6: f32, %arg7: f32):
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%5 = addf %arg5, %arg6 : f32
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linalg.yield %5 : f32
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} -> tensor<?x?x?xf32>
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return %4 : tensor<?x?x?xf32>
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}
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// CHECK-LABEL: func @indexed_generic_op_tensors
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// CHECK-SAME: %[[ARG0:[a-zA-Z0-9_]+]]: tensor<?x?x?xf32>
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// CHECK-SAME: %[[ARG1:[a-zA-Z0-9_]+]]: tensor<?x?x?xf32>
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// CHECK: %[[INIT:.+]] = linalg.init_tensor
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// CHECK: %[[TD0:.+]] = scf.for %{{.+}} to %{{.+}} step %{{.+}} iter_args(%[[TC0:.+]] = %[[INIT]]) -> (tensor<?x?x?xf32>) {
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// CHECK: %[[TD1:.+]] = scf.for %{{.+}} to %{{.+}} step %{{.+}} iter_args(%[[TC1:.+]] = %[[TC0]]) -> (tensor<?x?x?xf32>) {
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// CHECK: %[[TD2:.+]] = scf.for %{{.+}} to %{{.+}} step %{{.+}} iter_args(%[[TC2:.+]] = %[[TC1]]) -> (tensor<?x?x?xf32>) {
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// CHECK: %[[STARG0:.+]] = subtensor %[[ARG0]][{{.+}}] : tensor<?x?x?xf32> to tensor<?x?x?xf32>
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// CHECK: %[[STARG1:.+]] = subtensor %[[ARG1]][{{.+}}] : tensor<?x?x?xf32> to tensor<?x?x?xf32>
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// CHECK: %[[STARG2:.+]] = subtensor %[[TC2]][{{.+}}] : tensor<?x?x?xf32> to tensor<?x?x?xf32>
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// CHECK: %[[STRETURN:.+]] = linalg.indexed_generic
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// CHECK-SAME: ins(%[[STARG0]], %[[STARG1]] : tensor<?x?x?xf32>, tensor<?x?x?xf32>)
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// CHECK-SAME: outs(%[[STARG2]] : tensor<?x?x?xf32>)
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// CHECK: %[[TD:.+]] = subtensor_insert %[[STRETURN]] into %[[TC2]]
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// CHECK: scf.yield %[[TD]]
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// CHECK: }
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// CHECK: scf.yield %[[TD2]]
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// CHECK: }
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// CHECK: scf.yield %[[TD1]]
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// CHECK: }
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// CHECK: return %[[TD0]]
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