maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Refactor some of the encoding logic into a base class. This keeps us from having 

to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.

llvm-svn: 116362
This commit is contained in:
Bill Wendling 2010-10-12 23:06:54 +00:00
parent 78c0aeb4b3
commit 42200bcaea
1 changed files with 55 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

119
llvm/lib/Target/ARM/ARMInstrVFP.td
View File

@ -138,77 +138,68 @@ def VSTMS_UPD : AXSI4<(outs GPR:$wb), (ins addrmode4:$addr, pred:$p,
// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
// FIXME: Can these be placed into the base class?
class ADbI_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
dag iops, InstrItinClass itin, string opc, string asm,
list<dag> pattern>
: ADbI<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
// Instruction operands.
bits<5> Dd;
bits<5> Dn;
bits<5> Dm;
// Encode instruction operands.
let Inst{3-0} = Dm{3-0};
let Inst{5} = Dm{4};
let Inst{19-16} = Dn{3-0};
let Inst{7} = Dn{4};
let Inst{15-12} = Dd{3-0};
let Inst{22} = Dd{4};
}
class ASbIn_Encode<bits<5> opcod1, bits<2> opcod2, bit op6, bit op4, dag oops,
dag iops, InstrItinClass itin, string opc, string asm,
list<dag> pattern>
: ASbIn<opcod1, opcod2, op6, op4, oops, iops, itin, opc, asm, pattern> {
// Instruction operands.
bits<5> Sd;
bits<5> Sn;
bits<5> Sm;
// Encode instruction operands.
let Inst{3-0} = Sm{4-1};
let Inst{5} = Sm{0};
let Inst{19-16} = Sn{4-1};
let Inst{7} = Sn{0};
let Inst{15-12} = Sd{4-1};
let Inst{22} = Sd{0};
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// FP Binary Operations. // FP Binary Operations.
// //
def VADDD : ADbI<0b11100, 0b11, 0, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm), def VADDD : ADbI_Encode<0b11100, 0b11, 0, 0,
IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm", (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
[(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]> { IIC_fpALU64, "vadd", ".f64\t$Dd, $Dn, $Dm",
// Instruction operands. [(set DPR:$Dd, (fadd DPR:$Dn, (f64 DPR:$Dm)))]>;
bits<5> Dd;
bits<5> Dn;
bits<5> Dm;
// Encode instruction operands. def VADDS : ASbIn_Encode<0b11100, 0b11, 0, 0,
let Inst{3-0} = Dm{3-0}; (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
let Inst{5} = Dm{4}; IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm",
let Inst{19-16} = Dn{3-0}; [(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]>;
let Inst{7} = Dn{4};
let Inst{15-12} = Dd{3-0};
let Inst{22} = Dd{4};
}
def VADDS : ASbIn<0b11100, 0b11, 0, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm), def VSUBD : ADbI_Encode<0b11100, 0b11, 1, 0,
IIC_fpALU32, "vadd", ".f32\t$Sd, $Sn, $Sm", (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
[(set SPR:$Sd, (fadd SPR:$Sn, SPR:$Sm))]> { IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
// Instruction operands. [(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]>;
bits<5> Sd;
bits<5> Sn;
bits<5> Sm;
// Encode instruction operands. def VSUBS : ASbIn_Encode<0b11100, 0b11, 1, 0,
let Inst{3-0} = Sm{4-1}; (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
let Inst{5} = Sm{0}; IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
let Inst{19-16} = Sn{4-1}; [(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]>;
let Inst{7} = Sn{0};
let Inst{15-12} = Sd{4-1};
let Inst{22} = Sd{0};
}
def VSUBD : ADbI<0b11100, 0b11, 1, 0, (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm",
[(set DPR:$Dd, (fsub DPR:$Dn, (f64 DPR:$Dm)))]> {
// Instruction operands.
bits<5> Dd;
bits<5> Dn;
bits<5> Dm;
// Encode instruction operands.
let Inst{3-0} = Dm{3-0};
let Inst{5} = Dm{4};
let Inst{19-16} = Dn{3-0};
let Inst{7} = Dn{4};
let Inst{15-12} = Dd{3-0};
let Inst{22} = Dd{4};
}
def VSUBS : ASbIn<0b11100, 0b11, 1, 0, (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm",
[(set SPR:$Sd, (fsub SPR:$Sn, SPR:$Sm))]> {
// Instruction operands.
bits<5> Sd;
bits<5> Sn;
bits<5> Sm;
// Encode instruction operands.
let Inst{3-0} = Sm{4-1};
let Inst{5} = Sm{0};
let Inst{19-16} = Sn{4-1};
let Inst{7} = Sn{0};
let Inst{15-12} = Sd{4-1};
let Inst{22} = Sd{0};
}
def VDIVD : ADbI<0b11101, 0b00, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b), def VDIVD : ADbI<0b11101, 0b00, 0, 0, (outs DPR:$dst), (ins DPR:$a, DPR:$b),
IIC_fpDIV64, "vdiv", ".f64\t$dst, $a, $b", IIC_fpDIV64, "vdiv", ".f64\t$dst, $a, $b",