forked from OSchip/llvm-project
[X86] Added cmov target to memcmp test
As discussed by @spatel on D35067: "I added the cmov attribute to the 32-bit codegen test because it removes some noise for that file. I think the intent for the SSE vs no-SSE runs is to show the potential difference for the 16 and 32 byte cases rather than the lack of cmov (which has been available for all CPUs since SSE1, so that's why it shows up automatically with -mattr=sse2)." llvm-svn: 308309
This commit is contained in:
Simon Pilgrim
parent
40b66d646e
commit
420e5eadc2
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@ -1,8 +1,8 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86 --check-prefix=X86-NOSSE
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefix=X86 --check-prefix=X86-NOSSE
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=AVX2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX2
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; This tests codegen time inlining/optimization of memcmp
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; rdar://6480398
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@ -12,43 +12,21 @@
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declare i32 @memcmp(i8*, i8*, i64)
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define i32 @length2(i8* %X, i8* %Y) nounwind {
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; X86-NOSSE-LABEL: length2:
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; X86-NOSSE: # BB#0:
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NOSSE-NEXT: movzwl (%ecx), %ecx
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; X86-NOSSE-NEXT: movzwl (%eax), %eax
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; X86-NOSSE-NEXT: rolw $8, %cx
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; X86-NOSSE-NEXT: rolw $8, %ax
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; X86-NOSSE-NEXT: cmpw %ax, %cx
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; X86-NOSSE-NEXT: movl $-1, %eax
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; X86-NOSSE-NEXT: jae .LBB0_1
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; X86-NOSSE-NEXT: # BB#2:
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; X86-NOSSE-NEXT: je .LBB0_3
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; X86-NOSSE-NEXT: .LBB0_4:
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; X86-NOSSE-NEXT: retl
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; X86-NOSSE-NEXT: .LBB0_1:
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; X86-NOSSE-NEXT: movl $1, %eax
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; X86-NOSSE-NEXT: jne .LBB0_4
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; X86-NOSSE-NEXT: .LBB0_3:
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; X86-NOSSE-NEXT: xorl %eax, %eax
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; X86-NOSSE-NEXT: retl
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;
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; X86-SSE2-LABEL: length2:
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; X86-SSE2: # BB#0:
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; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE2-NEXT: movzwl (%ecx), %ecx
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; X86-SSE2-NEXT: movzwl (%eax), %eax
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; X86-SSE2-NEXT: rolw $8, %cx
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; X86-SSE2-NEXT: rolw $8, %ax
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; X86-SSE2-NEXT: xorl %edx, %edx
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; X86-SSE2-NEXT: cmpw %ax, %cx
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; X86-SSE2-NEXT: movl $-1, %ecx
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; X86-SSE2-NEXT: movl $1, %eax
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; X86-SSE2-NEXT: cmovbl %ecx, %eax
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; X86-SSE2-NEXT: cmovel %edx, %eax
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; X86-SSE2-NEXT: retl
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; X86-LABEL: length2:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movzwl (%ecx), %ecx
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; X86-NEXT: movzwl (%eax), %eax
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; X86-NEXT: rolw $8, %cx
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; X86-NEXT: rolw $8, %ax
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: cmpw %ax, %cx
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; X86-NEXT: movl $-1, %ecx
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; X86-NEXT: movl $1, %eax
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; X86-NEXT: cmovbl %ecx, %eax
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; X86-NEXT: cmovel %edx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: length2:
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; X64: # BB#0:
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@ -182,43 +160,21 @@ define i1 @length3_eq(i8* %X, i8* %Y) nounwind {
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}
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define i32 @length4(i8* %X, i8* %Y) nounwind {
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; X86-NOSSE-LABEL: length4:
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; X86-NOSSE: # BB#0:
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NOSSE-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NOSSE-NEXT: movl (%ecx), %ecx
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; X86-NOSSE-NEXT: movl (%eax), %eax
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; X86-NOSSE-NEXT: bswapl %ecx
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; X86-NOSSE-NEXT: bswapl %eax
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; X86-NOSSE-NEXT: cmpl %eax, %ecx
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; X86-NOSSE-NEXT: movl $-1, %eax
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; X86-NOSSE-NEXT: jae .LBB6_1
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; X86-NOSSE-NEXT: # BB#2:
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; X86-NOSSE-NEXT: je .LBB6_3
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; X86-NOSSE-NEXT: .LBB6_4:
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; X86-NOSSE-NEXT: retl
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; X86-NOSSE-NEXT: .LBB6_1:
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; X86-NOSSE-NEXT: movl $1, %eax
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; X86-NOSSE-NEXT: jne .LBB6_4
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; X86-NOSSE-NEXT: .LBB6_3:
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; X86-NOSSE-NEXT: xorl %eax, %eax
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; X86-NOSSE-NEXT: retl
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;
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; X86-SSE2-LABEL: length4:
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; X86-SSE2: # BB#0:
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; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE2-NEXT: movl (%ecx), %ecx
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; X86-SSE2-NEXT: movl (%eax), %eax
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; X86-SSE2-NEXT: bswapl %ecx
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; X86-SSE2-NEXT: bswapl %eax
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; X86-SSE2-NEXT: xorl %edx, %edx
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; X86-SSE2-NEXT: cmpl %eax, %ecx
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; X86-SSE2-NEXT: movl $-1, %ecx
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; X86-SSE2-NEXT: movl $1, %eax
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; X86-SSE2-NEXT: cmovbl %ecx, %eax
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; X86-SSE2-NEXT: cmovel %edx, %eax
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; X86-SSE2-NEXT: retl
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; X86-LABEL: length4:
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; X86: # BB#0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl (%ecx), %ecx
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; X86-NEXT: movl (%eax), %eax
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; X86-NEXT: bswapl %ecx
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; X86-NEXT: bswapl %eax
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: cmpl %eax, %ecx
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; X86-NEXT: movl $-1, %ecx
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; X86-NEXT: movl $1, %eax
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; X86-NEXT: cmovbl %ecx, %eax
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; X86-NEXT: cmovel %edx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: length4:
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; X64: # BB#0:
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