forked from OSchip/llvm-project
[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::selectSExti32/selectZExti32.
This helps us select W instructions in more cases. Most of the affected tests have had the sign_extend_inreg or AND folded into sextload/zextload. Differential Revision: https://reviews.llvm.org/D104079
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7836d058c7
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420bd5ee8e
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@ -1338,14 +1338,8 @@ bool RISCVDAGToDAGISel::selectSExti32(SDValue N, SDValue &Val) {
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Val = N.getOperand(0);
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return true;
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}
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// FIXME: Should we just call computeNumSignBits here?
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if (N.getOpcode() == ISD::AssertSext &&
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cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32)) {
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Val = N;
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return true;
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}
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if (N.getOpcode() == ISD::AssertZext &&
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cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32)) {
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MVT VT = N.getSimpleValueType();
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if (CurDAG->ComputeNumSignBits(N) > (VT.getSizeInBits() - 32)) {
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Val = N;
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return true;
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}
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@ -1361,9 +1355,9 @@ bool RISCVDAGToDAGISel::selectZExti32(SDValue N, SDValue &Val) {
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return true;
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}
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}
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// FIXME: Should we just call computeKnownBits here?
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if (N.getOpcode() == ISD::AssertZext &&
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cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32)) {
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MVT VT = N.getSimpleValueType();
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APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 32);
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if (CurDAG->MaskedValueIsZero(N, Mask)) {
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Val = N;
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return true;
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}
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@ -1029,7 +1029,7 @@ def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
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let Predicates = [HasStdExtZbb, IsRV64] in {
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def : PatGpr<riscv_clzw, CLZW>;
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def : PatGpr<riscv_ctzw, CTZW>;
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def : Pat<(i64 (ctpop (and GPR:$rs1, 0xFFFFFFFF))), (CPOPW GPR:$rs1)>;
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def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>;
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} // Predicates = [HasStdExtZbb, IsRV64]
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let Predicates = [HasStdExtZbp, IsRV64] in {
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@ -206,7 +206,7 @@ define double @fcvt_d_w_load(i32* %p) nounwind {
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; RV64IFD-LABEL: fcvt_d_w_load:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: lw a0, 0(a0)
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; RV64IFD-NEXT: fcvt.d.l ft0, a0
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; RV64IFD-NEXT: fcvt.d.w ft0, a0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%a = load i32, i32* %p
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@ -249,7 +249,7 @@ define double @fcvt_d_wu_load(i32* %p) nounwind {
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; RV64IFD-LABEL: fcvt_d_wu_load:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: lwu a0, 0(a0)
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; RV64IFD-NEXT: fcvt.d.lu ft0, a0
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; RV64IFD-NEXT: fcvt.d.wu ft0, a0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%a = load i32, i32* %p
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@ -207,7 +207,7 @@ define float @fcvt_s_w_load(i32* %p) nounwind {
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; RV64IF-LABEL: fcvt_s_w_load:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: lw a0, 0(a0)
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; RV64IF-NEXT: fcvt.s.l ft0, a0
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; RV64IF-NEXT: fcvt.s.w ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%a = load i32, i32* %p
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@ -242,7 +242,7 @@ define float @fcvt_s_wu_load(i32* %p) nounwind {
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; RV64IF-LABEL: fcvt_s_wu_load:
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; RV64IF: # %bb.0:
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; RV64IF-NEXT: lwu a0, 0(a0)
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; RV64IF-NEXT: fcvt.s.lu ft0, a0
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; RV64IF-NEXT: fcvt.s.wu ft0, a0
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; RV64IF-NEXT: fmv.x.w a0, ft0
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; RV64IF-NEXT: ret
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%a = load i32, i32* %p
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@ -855,14 +855,14 @@ define half @fcvt_h_si(i16 %a) nounwind {
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: slli a0, a0, 48
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; RV64IZFH-NEXT: srai a0, a0, 48
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; RV64IZFH-NEXT: fcvt.h.l fa0, a0
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; RV64IZFH-NEXT: fcvt.h.w fa0, a0
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: fcvt_h_si:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: slli a0, a0, 48
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; RV64IDZFH-NEXT: srai a0, a0, 48
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; RV64IDZFH-NEXT: fcvt.h.l fa0, a0
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; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
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; RV64IDZFH-NEXT: ret
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%1 = sitofp i16 %a to half
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ret half %1
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@ -914,7 +914,7 @@ define half @fcvt_h_ui(i16 %a) nounwind {
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; RV64IZFH-NEXT: lui a1, 16
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; RV64IZFH-NEXT: addiw a1, a1, -1
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; RV64IZFH-NEXT: and a0, a0, a1
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; RV64IZFH-NEXT: fcvt.h.lu fa0, a0
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; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: fcvt_h_ui:
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@ -922,7 +922,7 @@ define half @fcvt_h_ui(i16 %a) nounwind {
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; RV64IDZFH-NEXT: lui a1, 16
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; RV64IDZFH-NEXT: addiw a1, a1, -1
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; RV64IDZFH-NEXT: and a0, a0, a1
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; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0
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; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
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; RV64IDZFH-NEXT: ret
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%1 = uitofp i16 %a to half
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ret half %1
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@ -992,13 +992,13 @@ define half @fcvt_h_w_load(i32* %p) nounwind {
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; RV64IZFH-LABEL: fcvt_h_w_load:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: lw a0, 0(a0)
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; RV64IZFH-NEXT: fcvt.h.l fa0, a0
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; RV64IZFH-NEXT: fcvt.h.w fa0, a0
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: fcvt_h_w_load:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: lw a0, 0(a0)
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; RV64IDZFH-NEXT: fcvt.h.l fa0, a0
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; RV64IDZFH-NEXT: fcvt.h.w fa0, a0
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; RV64IDZFH-NEXT: ret
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%a = load i32, i32* %p
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%1 = sitofp i32 %a to half
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@ -1045,13 +1045,13 @@ define half @fcvt_h_wu_load(i32* %p) nounwind {
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; RV64IZFH-LABEL: fcvt_h_wu_load:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: lwu a0, 0(a0)
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; RV64IZFH-NEXT: fcvt.h.lu fa0, a0
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; RV64IZFH-NEXT: fcvt.h.wu fa0, a0
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; RV64IZFH-NEXT: ret
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;
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; RV64IDZFH-LABEL: fcvt_h_wu_load:
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; RV64IDZFH: # %bb.0:
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; RV64IDZFH-NEXT: lwu a0, 0(a0)
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; RV64IDZFH-NEXT: fcvt.h.lu fa0, a0
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; RV64IDZFH-NEXT: fcvt.h.wu fa0, a0
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; RV64IDZFH-NEXT: ret
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%a = load i32, i32* %p
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%1 = uitofp i32 %a to half
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@ -232,7 +232,7 @@ define i8 @srem8(i8 %a, i8 %b) nounwind {
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; RV64IM-NEXT: srai a1, a1, 56
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; RV64IM-NEXT: slli a0, a0, 56
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; RV64IM-NEXT: srai a0, a0, 56
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; RV64IM-NEXT: rem a0, a0, a1
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; RV64IM-NEXT: remw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i8 %a, %b
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ret i8 %1
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@ -328,7 +328,7 @@ define i16 @srem16(i16 %a, i16 %b) nounwind {
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; RV64IM-NEXT: srai a1, a1, 48
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; RV64IM-NEXT: slli a0, a0, 48
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; RV64IM-NEXT: srai a0, a0, 48
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; RV64IM-NEXT: rem a0, a0, a1
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; RV64IM-NEXT: remw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = srem i16 %a, %b
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ret i16 %1
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@ -1060,13 +1060,13 @@ define signext i32 @ctpop_i32_load(i32* %p) nounwind {
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; RV64IB-LABEL: ctpop_i32_load:
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; RV64IB: # %bb.0:
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; RV64IB-NEXT: lwu a0, 0(a0)
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; RV64IB-NEXT: cpop a0, a0
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; RV64IB-NEXT: cpopw a0, a0
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; RV64IB-NEXT: ret
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;
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; RV64IBB-LABEL: ctpop_i32_load:
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; RV64IBB: # %bb.0:
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; RV64IBB-NEXT: lwu a0, 0(a0)
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; RV64IBB-NEXT: cpop a0, a0
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; RV64IBB-NEXT: cpopw a0, a0
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; RV64IBB-NEXT: ret
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%a = load i32, i32* %p
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%1 = call i32 @llvm.ctpop.i32(i32 %a)
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