From 41e5ac4fa4a90f0d233f16d11763af68b735b8d7 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Wed, 14 Mar 2018 00:36:23 +0000 Subject: [PATCH] TargetMachine: Add address space to getPointerSize llvm-svn: 327467 --- llvm/include/llvm/Target/TargetMachine.h | 16 +++++++++++++++- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 6 ++++-- llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 6 +++--- llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp | 2 +- llvm/lib/Target/ARM/ARMInstructionSelector.cpp | 4 ++-- llvm/lib/Target/Sparc/SparcISelLowering.cpp | 2 +- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +- llvm/lib/Target/X86/X86LegalizerInfo.cpp | 4 ++-- 9 files changed, 30 insertions(+), 14 deletions(-) diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index 3f9f4e7c8258..6f5d86ec7464 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -138,7 +138,21 @@ public: /// Get the pointer size for this target. /// /// This is the only time the DataLayout in the TargetMachine is used. - unsigned getPointerSize() const { return DL.getPointerSize(); } + unsigned getPointerSize(unsigned AS) const { + return DL.getPointerSize(AS); + } + + unsigned getPointerSizeInBits(unsigned AS) const { + return DL.getPointerSizeInBits(AS); + } + + unsigned getProgramPointerSize() const { + return DL.getPointerSize(DL.getProgramAddressSpace()); + } + + unsigned getAllocaPointerSize() const { + return DL.getPointerSize(DL.getAllocaAddrSpace()); + } /// \brief Reset the target options based on the function's attributes. // FIXME: Remove TargetOptions that affect per-function code generation diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index 568d99269aae..6455b6343d25 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -215,7 +215,9 @@ const DataLayout &AsmPrinter::getDataLayout() const { // Do not use the cached DataLayout because some client use it without a Module // (llvm-dsymutil, llvm-dwarfdump). -unsigned AsmPrinter::getPointerSize() const { return TM.getPointerSize(); } +unsigned AsmPrinter::getPointerSize() const { + return TM.getPointerSize(0); // FIXME: Default address space +} const MCSubtargetInfo &AsmPrinter::getSubtargetInfo() const { assert(MF && "getSubtargetInfo requires a valid MachineFunction!"); @@ -979,7 +981,7 @@ void AsmPrinter::emitStackSizeSection(const MachineFunction &MF) { const MCSymbol *FunctionSymbol = getSymbol(&MF.getFunction()); uint64_t StackSize = FrameInfo.getStackSize(); - OutStreamer->EmitSymbolValue(FunctionSymbol, TM.getPointerSize()); + OutStreamer->EmitSymbolValue(FunctionSymbol, TM.getProgramPointerSize()); OutStreamer->EmitULEB128IntValue(StackSize); OutStreamer->PopSection(); diff --git a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp index 0e8a83cbe182..59b6c99f9969 100644 --- a/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp @@ -1318,7 +1318,7 @@ TypeIndex CodeViewDebug::lowerTypeArray(const DICompositeType *Ty) { DITypeRef ElementTypeRef = Ty->getBaseType(); TypeIndex ElementTypeIndex = getTypeIndex(ElementTypeRef); // IndexType is size_t, which depends on the bitness of the target. - TypeIndex IndexType = Asm->TM.getPointerSize() == 8 + TypeIndex IndexType = getPointerSizeInBytes() == 8 ? TypeIndex(SimpleTypeKind::UInt64Quad) : TypeIndex(SimpleTypeKind::UInt32Long); @@ -1526,8 +1526,8 @@ TypeIndex CodeViewDebug::lowerTypeMemberPointer(const DIDerivedType *Ty, assert(Ty->getTag() == dwarf::DW_TAG_ptr_to_member_type); TypeIndex ClassTI = getTypeIndex(Ty->getClassType()); TypeIndex PointeeTI = getTypeIndex(Ty->getBaseType(), Ty->getClassType()); - PointerKind PK = Asm->TM.getPointerSize() == 8 ? PointerKind::Near64 - : PointerKind::Near32; + PointerKind PK = getPointerSizeInBytes() == 8 ? PointerKind::Near64 + : PointerKind::Near32; bool IsPMF = isa(Ty->getBaseType()); PointerMode PM = IsPMF ? PointerMode::PointerToMemberFunction : PointerMode::PointerToDataMember; diff --git a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp index b2151eb49655..79fafa5497f9 100644 --- a/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp +++ b/llvm/lib/CodeGen/TargetFrameLoweringImpl.cpp @@ -100,7 +100,7 @@ unsigned TargetFrameLowering::getStackAlignmentSkew( // When HHVM function is called, the stack is skewed as the return address // is removed from the stack before we enter the function. if (LLVM_UNLIKELY(MF.getFunction().getCallingConv() == CallingConv::HHVM)) - return MF.getTarget().getPointerSize(); + return MF.getTarget().getAllocaPointerSize(); return 0; } diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp index f225ff824195..773b0dead18e 100644 --- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -511,7 +511,7 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB, bool UseMovt = STI.useMovt(MF); - unsigned Size = TM.getPointerSize(); + unsigned Size = TM.getPointerSize(0); unsigned Alignment = 4; auto addOpsForConstantPoolLoad = [&MF, Alignment, @@ -554,7 +554,7 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB, if (Indirect) MIB.addMemOperand(MF.getMachineMemOperand( MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad, - TM.getPointerSize(), Alignment)); + TM.getProgramPointerSize(), Alignment)); return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); } diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index f120c0214721..2e9390a82874 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1450,7 +1450,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI) : TargetLowering(TM), Subtarget(&STI) { - MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize()); + MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize(0)); // Instructions which use registers as conditionals examine all the // bits (as does the pseudo SELECT_CC expansion). I don't think it diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index c6bb86f93f1e..7dac303b3b32 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -76,7 +76,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) { SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, const SystemZSubtarget &STI) : TargetLowering(TM), Subtarget(STI) { - MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize()); + MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize(0)); // Set up the register classes. if (Subtarget.hasHighWord()) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 4d314721f660..1493f93b1d7b 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -103,7 +103,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87(); X86ScalarSSEf64 = Subtarget.hasSSE2(); X86ScalarSSEf32 = Subtarget.hasSSE1(); - MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize()); + MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0)); // Set up the TargetLowering object. diff --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp index bcf0ffb1bdfa..3a814d3daa81 100644 --- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp +++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp @@ -86,7 +86,7 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI, void X86LegalizerInfo::setLegalizerInfo32bit() { - const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8); + const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0)); const LLT s1 = LLT::scalar(1); const LLT s8 = LLT::scalar(8); const LLT s16 = LLT::scalar(16); @@ -169,7 +169,7 @@ void X86LegalizerInfo::setLegalizerInfo64bit() { if (!Subtarget.is64Bit()) return; - const LLT p0 = LLT::pointer(0, TM.getPointerSize() * 8); + const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0)); const LLT s1 = LLT::scalar(1); const LLT s8 = LLT::scalar(8); const LLT s16 = LLT::scalar(16);