forked from OSchip/llvm-project
[GlobalISel][InlineAsm] Fix matching input constraints to mem operand
Mark matching input constraint to mem operand as not supported. Differential Revision: https://reviews.llvm.org/D83235
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@ -406,6 +406,18 @@ bool InlineAsmLowering::lowerInlineAsm(
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InstFlagIdx += getNumOpRegs(*Inst, InstFlagIdx) + 1;
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assert(getNumOpRegs(*Inst, InstFlagIdx) == 1 && "Wrong flag");
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unsigned MatchedOperandFlag = Inst->getOperand(InstFlagIdx).getImm();
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if (InlineAsm::isMemKind(MatchedOperandFlag)) {
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LLVM_DEBUG(dbgs() << "Matching input constraint to mem operand not "
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"supported. This should be target specific.\n");
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return false;
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}
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if (!InlineAsm::isRegDefKind(MatchedOperandFlag) &&
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!InlineAsm::isRegDefEarlyClobberKind(MatchedOperandFlag)) {
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LLVM_DEBUG(dbgs() << "Unknown matching constraint\n");
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return false;
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}
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// We want to tie input to register in next operand.
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unsigned DefRegIdx = InstFlagIdx + 1;
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Register Def = Inst->getOperand(DefRegIdx).getReg();
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@ -244,6 +244,16 @@ define i8 @scalable_call(i8* %addr) #1 {
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ret i8 %res
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}
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to translate instruction{{.*}}asm_indirect_output
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; FALLBACK-WITH-REPORT-OUT-LABEL: asm_indirect_output
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define void @asm_indirect_output() {
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entry:
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%ap = alloca i8*, align 8
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%0 = load i8*, i8** %ap, align 8
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call void asm sideeffect "", "=*r|m,0,~{memory}"(i8** %ap, i8* %0)
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ret void
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}
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attributes #1 = { "target-features"="+sve" }
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declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 %pattern)
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