forked from OSchip/llvm-project
[AMDGPU] Increased vector length for global/constant loads.
Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache; loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords. Author: FarhanaAleen Reviewed By: rampitec Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D43275 llvm-svn: 325518
This commit is contained in:
Mark Searles
parent
bc35f069f4
commit
419bdab759
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@ -233,12 +233,38 @@ unsigned AMDGPUTTIImpl::getMinVectorRegisterBitWidth() const {
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return 32;
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}
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unsigned AMDGPUTTIImpl::getLoadVectorFactor(unsigned VF, unsigned LoadSize,
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unsigned ChainSizeInBytes,
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VectorType *VecTy) const {
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unsigned VecRegBitWidth = VF * LoadSize;
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if (VecRegBitWidth > 128 && VecTy->getScalarSizeInBits() < 32)
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// TODO: Support element-size less than 32bit?
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return 128 / LoadSize;
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return VF;
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}
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unsigned AMDGPUTTIImpl::getStoreVectorFactor(unsigned VF, unsigned StoreSize,
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unsigned ChainSizeInBytes,
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VectorType *VecTy) const {
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unsigned VecRegBitWidth = VF * StoreSize;
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if (VecRegBitWidth > 128)
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return 128 / StoreSize;
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return VF;
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}
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unsigned AMDGPUTTIImpl::getLoadStoreVecRegBitWidth(unsigned AddrSpace) const {
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AMDGPUAS AS = ST->getAMDGPUAS();
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if (AddrSpace == AS.GLOBAL_ADDRESS ||
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AddrSpace == AS.CONSTANT_ADDRESS ||
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AddrSpace == AS.CONSTANT_ADDRESS_32BIT ||
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AddrSpace == AS.FLAT_ADDRESS)
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AddrSpace == AS.CONSTANT_ADDRESS_32BIT) {
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if (ST->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
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return 128;
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return 512;
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}
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if (AddrSpace == AS.FLAT_ADDRESS)
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return 128;
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if (AddrSpace == AS.LOCAL_ADDRESS ||
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AddrSpace == AS.REGION_ADDRESS)
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@ -118,6 +118,12 @@ public:
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unsigned getNumberOfRegisters(bool Vector) const;
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unsigned getRegisterBitWidth(bool Vector) const;
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unsigned getMinVectorRegisterBitWidth() const;
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unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
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unsigned ChainSizeInBytes,
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VectorType *VecTy) const;
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unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
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unsigned ChainSizeInBytes,
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VectorType *VecTy) const;
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unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
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bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes,
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@ -0,0 +1,37 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; Tests whether a load chain of 8 constants gets vectorized into a wider load.
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; FUNC-LABEL: {{^}}constant_load_v8f32:
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; GCN: s_load_dwordx8
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; EG: VTX_READ_128
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; EG: VTX_READ_128
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define amdgpu_kernel void @constant_load_v8f32(float addrspace(4)* noalias nocapture readonly %weights, float addrspace(1)* noalias nocapture %out_ptr) {
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entry:
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%out_ptr.promoted = load float, float addrspace(1)* %out_ptr, align 4
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%tmp = load float, float addrspace(4)* %weights, align 4
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%add = fadd float %tmp, %out_ptr.promoted
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%arrayidx.1 = getelementptr inbounds float, float addrspace(4)* %weights, i64 1
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%tmp1 = load float, float addrspace(4)* %arrayidx.1, align 4
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%add.1 = fadd float %tmp1, %add
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%arrayidx.2 = getelementptr inbounds float, float addrspace(4)* %weights, i64 2
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%tmp2 = load float, float addrspace(4)* %arrayidx.2, align 4
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%add.2 = fadd float %tmp2, %add.1
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%arrayidx.3 = getelementptr inbounds float, float addrspace(4)* %weights, i64 3
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%tmp3 = load float, float addrspace(4)* %arrayidx.3, align 4
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%add.3 = fadd float %tmp3, %add.2
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%arrayidx.4 = getelementptr inbounds float, float addrspace(4)* %weights, i64 4
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%tmp4 = load float, float addrspace(4)* %arrayidx.4, align 4
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%add.4 = fadd float %tmp4, %add.3
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%arrayidx.5 = getelementptr inbounds float, float addrspace(4)* %weights, i64 5
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%tmp5 = load float, float addrspace(4)* %arrayidx.5, align 4
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%add.5 = fadd float %tmp5, %add.4
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%arrayidx.6 = getelementptr inbounds float, float addrspace(4)* %weights, i64 6
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%tmp6 = load float, float addrspace(4)* %arrayidx.6, align 4
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%add.6 = fadd float %tmp6, %add.5
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%arrayidx.7 = getelementptr inbounds float, float addrspace(4)* %weights, i64 7
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%tmp7 = load float, float addrspace(4)* %arrayidx.7, align 4
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%add.7 = fadd float %tmp7, %add.6
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store float %add.7, float addrspace(1)* %out_ptr, align 4
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ret void
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}
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@ -13,3 +13,36 @@ define amdgpu_kernel void @constant_load_f64(double addrspace(1)* %out, double a
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}
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attributes #0 = { nounwind }
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; Tests whether a load-chain of 8 constants of 64bit each gets vectorized into a wider load.
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; FUNC-LABEL: {{^}}constant_load_2v4f64:
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; GCN: s_load_dwordx16
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define amdgpu_kernel void @constant_load_2v4f64(double addrspace(4)* noalias nocapture readonly %weights, double addrspace(1)* noalias nocapture %out_ptr) {
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entry:
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%out_ptr.promoted = load double, double addrspace(1)* %out_ptr, align 4
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%tmp = load double, double addrspace(4)* %weights, align 4
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%add = fadd double %tmp, %out_ptr.promoted
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%arrayidx.1 = getelementptr inbounds double, double addrspace(4)* %weights, i64 1
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%tmp1 = load double, double addrspace(4)* %arrayidx.1, align 4
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%add.1 = fadd double %tmp1, %add
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%arrayidx.2 = getelementptr inbounds double, double addrspace(4)* %weights, i64 2
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%tmp2 = load double, double addrspace(4)* %arrayidx.2, align 4
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%add.2 = fadd double %tmp2, %add.1
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%arrayidx.3 = getelementptr inbounds double, double addrspace(4)* %weights, i64 3
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%tmp3 = load double, double addrspace(4)* %arrayidx.3, align 4
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%add.3 = fadd double %tmp3, %add.2
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%arrayidx.4 = getelementptr inbounds double, double addrspace(4)* %weights, i64 4
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%tmp4 = load double, double addrspace(4)* %arrayidx.4, align 4
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%add.4 = fadd double %tmp4, %add.3
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%arrayidx.5 = getelementptr inbounds double, double addrspace(4)* %weights, i64 5
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%tmp5 = load double, double addrspace(4)* %arrayidx.5, align 4
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%add.5 = fadd double %tmp5, %add.4
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%arrayidx.6 = getelementptr inbounds double, double addrspace(4)* %weights, i64 6
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%tmp6 = load double, double addrspace(4)* %arrayidx.6, align 4
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%add.6 = fadd double %tmp6, %add.5
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%arrayidx.7 = getelementptr inbounds double, double addrspace(4)* %weights, i64 7
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%tmp7 = load double, double addrspace(4)* %arrayidx.7, align 4
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%add.7 = fadd double %tmp7, %add.6
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store double %add.7, double addrspace(1)* %out_ptr, align 4
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ret void
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}
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global | FileCheck --check-prefix=GCN %s
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; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -amdgpu-load-store-vectorizer=0 | FileCheck --check-prefix=GCN %s
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; Check that the waitcnt insertion algorithm correctly propagates wait counts
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; from before a loop to the loop header.
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