forked from OSchip/llvm-project
new nodes should be added to the worklist, not old nodes.
llvm-svn: 62359
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5d7813cb2d
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41828cdb0a
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@ -3358,7 +3358,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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: DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
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: DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
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LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
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LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
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EVT, LN0->isVolatile(), NewAlign);
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EVT, LN0->isVolatile(), NewAlign);
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AddToWorkList(N);
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AddToWorkList(Load.Node);
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if (CombineSRL) {
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if (CombineSRL) {
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WorkListRemover DeadNodes(*this);
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WorkListRemover DeadNodes(*this);
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DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
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DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1),
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@ -3366,6 +3366,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) {
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CombineTo(N->getOperand(0).getNode(), Load);
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CombineTo(N->getOperand(0).getNode(), Load);
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} else
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} else
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CombineTo(N0.getNode(), Load, Load.getValue(1));
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CombineTo(N0.getNode(), Load, Load.getValue(1));
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if (ShAmt) {
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if (ShAmt) {
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if (Opc == ISD::SIGN_EXTEND_INREG)
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if (Opc == ISD::SIGN_EXTEND_INREG)
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return DAG.getNode(Opc, VT, Load, N->getOperand(1));
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return DAG.getNode(Opc, VT, Load, N->getOperand(1));
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