forked from OSchip/llvm-project
ARM: add fstmx and fldmx instructions for assembly
These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. llvm-svn: 183011
This commit is contained in:
Tim Northover
parent
ab8128b01d
commit
4173e29a98
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@ -1389,7 +1389,6 @@ class ADI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
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let Inst{15-12} = Dd{3-0};
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let Inst{7-0} = addr{7-0}; // imm8
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-24} = opcod1;
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let Inst{21-20} = opcod2;
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let Inst{11-9} = 0b101;
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@ -1415,7 +1414,6 @@ class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
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let Inst{15-12} = Sd{4-1};
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let Inst{7-0} = addr{7-0}; // imm8
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-24} = opcod1;
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let Inst{21-20} = opcod2;
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let Inst{11-9} = 0b101;
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@ -1437,6 +1435,28 @@ class PseudoVFPLdStM<dag oops, dag iops, InstrItinClass itin, string cstr,
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}
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// Load / store multiple
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// Unknown precision
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class AXXI4<dag oops, dag iops, IndexMode im,
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string asm, string cstr, list<dag> pattern>
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: VFPXI<oops, iops, AddrMode4, 4, im,
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VFPLdStFrm, NoItinerary, asm, cstr, pattern> {
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// Instruction operands.
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bits<4> Rn;
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bits<13> regs;
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// Encode instruction operands.
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let Inst{19-16} = Rn;
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let Inst{22} = 0;
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let Inst{15-12} = regs{11-8};
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let Inst{7-1} = regs{7-1};
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let Inst{27-25} = 0b110;
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let Inst{11-8} = 0b1011;
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let Inst{0} = 1;
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}
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// Double precision
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class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: VFPXI<oops, iops, AddrMode4, 4, im,
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@ -1449,14 +1469,15 @@ class AXDI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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let Inst{19-16} = Rn;
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let Inst{22} = regs{12};
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let Inst{15-12} = regs{11-8};
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let Inst{7-0} = regs{7-0};
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let Inst{7-1} = regs{7-1};
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-25} = 0b110;
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let Inst{11-9} = 0b101;
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let Inst{8} = 1; // Double precision
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let Inst{0} = 0;
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}
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// Single Precision
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class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: VFPXI<oops, iops, AddrMode4, 4, im,
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@ -1471,7 +1492,6 @@ class AXSI4<dag oops, dag iops, IndexMode im, InstrItinClass itin,
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let Inst{15-12} = regs{12-9};
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let Inst{7-0} = regs{7-0};
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// TODO: Mark the instructions with the appropriate subtarget info.
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let Inst{27-25} = 0b110;
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let Inst{11-9} = 0b101;
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let Inst{8} = 0; // Single precision
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@ -224,7 +224,36 @@ defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
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defm : VFPDTAnyInstAlias<"vpop${p}", "$r",
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(VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>;
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// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
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// FLDMX, FSTMX - Load and store multiple unknown precision registers for
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// pre-armv6 cores.
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// These instruction are deprecated so we don't want them to get selected.
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multiclass vfp_ldstx_mult<string asm, bit L_bit> {
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// Unknown precision
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def XIA :
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AXXI4<(outs), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
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IndexModeNone, !strconcat(asm, "iax${p}\t$Rn, $regs"), "", []> {
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let Inst{24-23} = 0b01; // Increment After
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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}
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def XIA_UPD :
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AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
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IndexModeUpd, !strconcat(asm, "iax${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b01; // Increment After
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let Inst{21} = 1; // Writeback
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let Inst{20} = L_bit;
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}
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def XDB_UPD :
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AXXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, dpr_reglist:$regs, variable_ops),
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IndexModeUpd, !strconcat(asm, "dbx${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b10; // Decrement Before
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let Inst{21} = 1;
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let Inst{20} = L_bit;
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}
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}
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defm FLDM : vfp_ldstx_mult<"fldm", 1>;
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defm FSTM : vfp_ldstx_mult<"fstm", 0>;
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//===----------------------------------------------------------------------===//
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// FP Binary Operations.
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@ -1150,6 +1150,13 @@ static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
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unsigned Vd = fieldFromInstruction(Val, 8, 5);
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unsigned regs = fieldFromInstruction(Val, 0, 8);
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// In case of unpredictable encoding, tweak the operands.
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if (regs == 0 || (Vd + regs) > 32) {
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regs = Vd + regs > 32 ? 32 - Vd : regs;
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regs = std::max( 1u, regs);
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S = MCDisassembler::SoftFail;
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}
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if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
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return MCDisassembler::Fail;
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for (unsigned i = 0; i < (regs - 1); ++i) {
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@ -1165,9 +1172,15 @@ static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
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DecodeStatus S = MCDisassembler::Success;
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unsigned Vd = fieldFromInstruction(Val, 8, 5);
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unsigned regs = fieldFromInstruction(Val, 0, 8);
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unsigned regs = fieldFromInstruction(Val, 1, 7);
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regs = regs >> 1;
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// In case of unpredictable encoding, tweak the operands.
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if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
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regs = Vd + regs > 32 ? 32 - Vd : regs;
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regs = std::max( 1u, regs);
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regs = std::min(16u, regs);
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S = MCDisassembler::SoftFail;
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}
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if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
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return MCDisassembler::Fail;
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@ -289,6 +289,20 @@
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vstmia r1, {s2,s3-s6,s7}
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vstmdb sp!, {q4-q7}
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fldmiax r5!, {d0-d2}
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fldmiaxeq r0, {d4,d5}
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fldmdbxne r5!, {d4,d5,d6}
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@ CHECK: fldmiax r5!, {d0, d1, d2} @ encoding: [0x07,0x0b,0xb5,0xec]
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@ CHECK: fldmiaxeq r0, {d4, d5} @ encoding: [0x05,0x4b,0x90,0x0c]
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@ CHECK: fldmdbxne r5!, {d4, d5, d6} @ encoding: [0x07,0x4b,0x35,0x1d]
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fstmiax r5!, {d0-d7}
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fstmiaxeq r4, {d8,d9}
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fstmdbxne r7!, {d2-d4}
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@ CHECK: fstmiax r5!, {d0, d1, d2, d3, d4, d5, d6, d7} @ encoding: [0x11,0x0b,0xa5,0xec]
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@ CHECK: fstmiaxeq r4, {d8, d9} @ encoding: [0x05,0x8b,0x84,0x0c]
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@ CHECK: fstmdbxne r7!, {d2, d3, d4} @ encoding: [0x07,0x2b,0x27,0x1d]
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@ CHECK: vcvtr.s32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbd,0xee]
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@ CHECK: vcvtr.s32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbd,0xee]
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@ CHECK: vcvtr.u32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbc,0xee]
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@ -221,6 +221,20 @@
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# CHECK: vldmdbeq r5!, {s21, s22, s23}
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# CHECK: vldmdbeq r7!, {d14, d15, d16, d17}
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0x0d 0x4b 0x96 0x0c
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0x0f 0x3b 0xb7 0x0c
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0x09 0x1b 0x38 0xed
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# CHECK: fldmiaxeq r6, {d4, d5, d6, d7, d8, d9}
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# CHECK: fldmiaxeq r7!, {d3, d4, d5, d6, d7, d8, d9}
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# CHECK: fldmdbx r8!, {d1, d2, d3, d4}
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0x07 0x2b 0x83 0xec
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0x05 0x5b 0xa3 0x0c
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0x0f 0x3b 0x20 0x1d
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# CHECK: fstmiax r3, {d2, d3, d4}
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# CHECK: fstmiaxeq r3!, {d5, d6}
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# CHECK: fstmdbxne r0!, {d3, d4, d5, d6, d7, d8, d9}
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0x04 0x7a 0xa6 0x0c
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0x0c 0xfb 0xa4 0x0c
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0x03 0xaa 0xf8 0x0c
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@ -0,0 +1,8 @@
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# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | FileCheck %s -check-prefix=CHECK-WARN
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# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | FileCheck %s
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# offset=1
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# CHECK-WARN: potentially undefined
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# CHECK-WARN: 0x01 0xdb 0x84 0xec
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# CHECK: fstmiax r4, {d13}
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0x01 0xdb 0x84 0xec
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