forked from OSchip/llvm-project
parent
9a7f4b76e5
commit
4167bb9346
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@ -198,7 +198,6 @@ def DINS : InsBase<7, "dins", CPU64Regs>;
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def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
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def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
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"dsll\t$rd, $rt, 32", [], IIAlu>;
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"dsll\t$rd, $rt, 32", [], IIAlu>;
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def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
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def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
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"sll\t$rd, $rt, 0", [], IIAlu>;
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"sll\t$rd, $rt, 0", [], IIAlu>;
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let isCodeGenOnly = 1 in
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let isCodeGenOnly = 1 in
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