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Revert ARM Scheduler Model: Add resources instructions, map resources 

This reverts commit r177968. It is causing failures in a local build bot.

"fatal error: error in backend: Expected a variant SchedClass"

Original commit message:
Move the CortexA9 resources into the CortexA9 SchedModel namespace. Define
resource mappings under the CortexA9 SchedModel. Define resources and mappings
for the SwiftModel.

llvm-svn: 178028
This commit is contained in:
Arnold Schwaighofer 2013-03-26 15:14:04 +00:00
parent c3048de5ac
commit 414ef565bb
4 changed files with 24 additions and 70 deletions
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45
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -1010,8 +1010,7 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc,
let isReMaterializable = 1 in {
def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
iii, opc, "\t$Rd, $Rn, $imm",
[(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
Sched<[WriteALU, ReadAdvanceALU]> {
[(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
@ -1023,8 +1022,7 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc,
}
def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
iir, opc, "\t$Rd, $Rn, $Rm",
[(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
Sched<[WriteALU, ReadAdvanceALU, ReadAdvanceALU]> {
[(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
@ -1039,8 +1037,7 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc,
def rsi : AsI1<opcod, (outs GPR:$Rd),
(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
iis, opc, "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]>,
Sched<[WriteALUsi, ReadAdvanceALU]> {
[(set GPR:$Rd, (opnode GPR:$Rn, so_reg_imm:$shift))]> {
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
@ -1055,8 +1052,7 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc,
def rsr : AsI1<opcod, (outs GPR:$Rd),
(ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
iis, opc, "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]>,
Sched<[WriteALUsr, ReadAdvanceALUsr]> {
[(set GPR:$Rd, (opnode GPR:$Rn, so_reg_reg:$shift))]> {
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
@ -1083,8 +1079,7 @@ multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
let isReMaterializable = 1 in {
def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
iii, opc, "\t$Rd, $Rn, $imm",
[(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
Sched<[WriteALU, ReadAdvanceALU]> {
[(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]> {
bits<4> Rd;
bits<4> Rn;
bits<12> imm;
@ -1096,8 +1091,7 @@ multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
}
def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
iir, opc, "\t$Rd, $Rn, $Rm",
[/* pattern left blank */]>,
Sched<[WriteALU, ReadAdvanceALU, ReadAdvanceALU]> {
[/* pattern left blank */]> {
bits<4> Rd;
bits<4> Rn;
bits<4> Rm;
@ -1111,8 +1105,7 @@ multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
def rsi : AsI1<opcod, (outs GPR:$Rd),
(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
iis, opc, "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]>,
Sched<[WriteALUsi, ReadAdvanceALU]> {
[(set GPR:$Rd, (opnode so_reg_imm:$shift, GPR:$Rn))]> {
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
@ -1127,8 +1120,7 @@ multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
def rsr : AsI1<opcod, (outs GPR:$Rd),
(ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
iis, opc, "\t$Rd, $Rn, $shift",
[(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]>,
Sched<[WriteALUsr, ReadAdvanceALUsr]> {
[(set GPR:$Rd, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
bits<4> Rd;
bits<4> Rn;
bits<12> shift;
@ -1153,28 +1145,24 @@ multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
bit Commutable = 0> {
def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
4, iii,
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
Sched<[WriteALU, ReadAdvanceALU]>;
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
4, iir,
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
Sched<[WriteALU, ReadAdvanceALU, ReadAdvanceALU]> {
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
let isCommutable = Commutable;
}
def rsi : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
4, iis,
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
so_reg_imm:$shift))]>,
Sched<[WriteALUsi, ReadAdvanceALU]>;
so_reg_imm:$shift))]>;
def rsr : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
4, iis,
[(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
so_reg_reg:$shift))]>,
Sched<[WriteALUSsr, ReadAdvanceALUsr]>;
so_reg_reg:$shift))]>;
}
}
@ -1186,22 +1174,19 @@ multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
bit Commutable = 0> {
def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
4, iii,
[(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
Sched<[WriteALU, ReadAdvanceALU]>;
[(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
def rsi : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
4, iis,
[(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
GPR:$Rn))]>,
Sched<[WriteALUsi, ReadAdvanceALU]>;
GPR:$Rn))]>;
def rsr : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
4, iis,
[(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
GPR:$Rn))]>,
Sched<[WriteALUSsr, ReadAdvanceALUsr]>;
GPR:$Rn))]>;
}
}

7
llvm/lib/Target/ARM/ARMSchedule.td
View File

@ -64,13 +64,6 @@ def WriteALUsr : SchedWrite; // Shift by register.
def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
def ReadAdvanceALUsr : SchedRead; // Some operands are read later.
// Define TII for use in SchedVariant Predicates.
def : PredicateProlog<[{
const ARMBaseInstrInfo *TII =
static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
(void)TII;
}]>;
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for ARM
//

19
llvm/lib/Target/ARM/ARMScheduleA9.td
View File

@ -1898,8 +1898,6 @@ def CortexA9Model : SchedMachineModel {
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available.
let SchedModel = CortexA9Model in {
def A9UnitALU : ProcResource<2>;
def A9UnitMul : ProcResource<1> { let Super = A9UnitALU; }
def A9UnitAGU : ProcResource<1>;
@ -2005,6 +2003,13 @@ foreach NumCycles = 2-8 in {
def A9WriteCycle#NumCycles : WriteSequence<[A9WriteCycle1], NumCycles>;
} // foreach NumCycles
// Define TII for use in SchedVariant Predicates.
def : PredicateProlog<[{
const ARMBaseInstrInfo *TII =
static_cast<const ARMBaseInstrInfo*>(SchedModel->getInstrInfo());
(void)TII;
}]>;
// Define address generation sequences and predicates for 8 flavors of LDMs.
foreach NumAddr = 1-8 in {
@ -2274,6 +2279,7 @@ def A9Read4 : SchedReadAdvance<3>;
// This table follows the ARM Cortex-A9 Technical Reference Manuals,
// mostly in order.
let SchedModel = CortexA9Model in {
def :ItinRW<[A9WriteI], [IIC_iMOVi,IIC_iMOVr,IIC_iMOVsi,
IIC_iMVNi,IIC_iMVNsi,
@ -2480,13 +2486,4 @@ def :ItinRW<[A9WriteV9, A9Read3, A9Read2], [IIC_VMACD, IIC_VFMACD]>;
def :ItinRW<[A9WriteV10, A9Read3, A9Read2], [IIC_VMACQ, IIC_VFMACQ]>;
def :ItinRW<[A9WriteV9, A9Read2, A9Read2], [IIC_VRECSD]>;
def :ItinRW<[A9WriteV10, A9Read2, A9Read2], [IIC_VRECSQ]>;
// New (incomplete) model mappings that don't rely on itinerary mappings.
def : SchedAlias<WriteALU, A9WriteA>;
def : SchedAlias<WriteALUsi, A9WriteAsi>;
def : SchedAlias<WriteALUsr, A9WriteAsr>;
def : SchedAlias<WriteALUSsr, A9WriteAsr>;
def : SchedAlias<ReadAdvanceALU, A9ReadA>;
def : SchedAlias<ReadAdvanceALUsr, A9ReadA>;
} // SchedModel = CortexA9Model

23
llvm/lib/Target/ARM/ARMScheduleSwift.td
View File

@ -1078,29 +1078,8 @@ def SwiftModel : SchedMachineModel {
let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
let MinLatency = 0; // Data dependencies are allowed within dispatch groups.
let LoadLatency = 3;
let MispredictPenalty = 14; // A branch direction mispredict.
let Itineraries = SwiftItineraries;
}
// Swift resource mapping.
let SchedModel = SwiftModel in {
// Processor resources.
def SwiftUnitP01 : ProcResource<2>; // ALU unit.
def SwiftUnitP0 : ProcResource<1> { let Super = SwiftUnitP01; } // Mul unit.
def SwiftUnitP1 : ProcResource<1> { let Super = SwiftUnitP01; } // Br unit.
def SwiftUnitP2 : ProcResource<1>; // LS unit.
def SwiftUnitDiv : ProcResource<1>;
// 4.2.4 Arithmetic and Logical.
// ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
// AND,BIC, EOR,ORN,ORR
// CLZ,RBIT,REV,REV16,REVSH,PKH
// Single cycle.
def : WriteRes<WriteALU, [SwiftUnitP01]>;
def : WriteRes<WriteALUsi, [SwiftUnitP01]>;
def : WriteRes<WriteALUsr, [SwiftUnitP01]>;
def : WriteRes<WriteALUSsr, [SwiftUnitP01]>;
def : ReadAdvance<ReadAdvanceALU, 0>;
def : ReadAdvance<ReadAdvanceALUsr, 2>;
}
// TODO: Add Swift processor and scheduler resources.