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[X86] Add HRESET instruction. 

For more details about these instructions, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D89102
This commit is contained in:
Wang, Pengfei 2020-10-13 08:42:46 +08:00
parent ec2c2ad2a2
commit 412cdcf2ed
24 changed files with 141 additions and 1 deletions
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2
clang/docs/ClangCommandLineReference.rst
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@ -3261,6 +3261,8 @@ X86
.. option:: -mgfni, -mno-gfni
.. option:: -mhreset, -mno-hreset
.. option:: -minvpcid, -mno-invpcid
.. option:: -mkl, -mno-kl

2
clang/include/clang/Driver/Options.td
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@ -3260,6 +3260,8 @@ def minvpcid : Flag<["-"], "minvpcid">, Group<m_x86_Features_Group>;
def mno_invpcid : Flag<["-"], "mno-invpcid">, Group<m_x86_Features_Group>;
def mgfni : Flag<["-"], "mgfni">, Group<m_x86_Features_Group>;
def mno_gfni : Flag<["-"], "mno-gfni">, Group<m_x86_Features_Group>;
def mhreset : Flag<["-"], "mhreset">, Group<m_x86_Features_Group>;
def mno_hreset : Flag<["-"], "mno-hreset">, Group<m_x86_Features_Group>;
def mkl : Flag<["-"], "mkl">, Group<m_x86_Features_Group>;
def mno_kl : Flag<["-"], "mno-kl">, Group<m_x86_Features_Group>;
def mwidekl : Flag<["-"], "mwidekl">, Group<m_x86_Features_Group>;

6
clang/lib/Basic/Targets/X86.cpp
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@ -298,6 +298,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasINVPCID = true;
} else if (Feature == "+enqcmd") {
HasENQCMD = true;
} else if (Feature == "+hreset") {
HasHRESET = true;
} else if (Feature == "+amx-bf16") {
HasAMXBF16 = true;
} else if (Feature == "+amx-int8") {
@ -712,6 +714,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__INVPCID__");
if (HasENQCMD)
Builder.defineMacro("__ENQCMD__");
if (HasHRESET)
Builder.defineMacro("__HRESET__");
if (HasAMXTILE)
Builder.defineMacro("__AMXTILE__");
if (HasAMXINT8)
@ -848,6 +852,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("fsgsbase", true)
.Case("fxsr", true)
.Case("gfni", true)
.Case("hreset", true)
.Case("invpcid", true)
.Case("kl", true)
.Case("widekl", true)
@ -936,6 +941,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("fsgsbase", HasFSGSBASE)
.Case("fxsr", HasFXSR)
.Case("gfni", HasGFNI)
.Case("hreset", HasHRESET)
.Case("invpcid", HasINVPCID)
.Case("kl", HasKL)
.Case("widekl", HasWIDEKL)

1
clang/lib/Basic/Targets/X86.h
View File

@ -129,6 +129,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasENQCMD = false;
bool HasKL = false; // For key locker
bool HasWIDEKL = false; // For wide key locker
bool HasHRESET = false;
bool HasAMXTILE = false;
bool HasAMXINT8 = false;
bool HasAMXBF16 = false;

2
clang/lib/Headers/CMakeLists.txt
View File

@ -65,6 +65,7 @@ set(files
fmaintrin.h
fxsrintrin.h
gfniintrin.h
hresetintrin.h
htmintrin.h
htmxlintrin.h
ia32intrin.h
@ -124,6 +125,7 @@ set(files
wmmintrin.h
__wmmintrin_aes.h
__wmmintrin_pclmul.h
x86gprintrin.h
x86intrin.h
xmmintrin.h
xopintrin.h

1
clang/lib/Headers/cpuid.h
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@ -196,6 +196,7 @@
/* Features in %eax for leaf 7 sub-leaf 1 */
#define bit_AVX512BF16 0x00000020
#define bit_HRESET 0x00400000
/* Features in %eax for leaf 13 sub-leaf 1 */
#define bit_XSAVEOPT 0x00000001

49
clang/lib/Headers/hresetintrin.h Normal file
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@ -0,0 +1,49 @@
/*===---------------- hresetintrin.h - HRESET intrinsics -------------------===
*
* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
* See https://llvm.org/LICENSE.txt for license information.
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
*
*===-----------------------------------------------------------------------===
*/
#ifndef __X86GPRINTRIN_H
#error "Never use <hresetintrin.h> directly; include <x86gprintrin.h> instead."
#endif
#ifndef __HRESETINTRIN_H
#define __HRESETINTRIN_H
#if __has_extension(gnu_asm)
/* Define the default attributes for the functions in this file. */
#define __DEFAULT_FN_ATTRS \
__attribute__((__always_inline__, __nodebug__, __target__("hreset")))
/// Provides a hint to the processor to selectively reset the prediction
/// history of the current logical processor specified by a 32-bit integer
/// value \a __eax.
///
/// This intrinsic corresponds to the <c> HRESET </c> instruction.
///
/// \operation
/// IF __eax == 0
/// // nop
/// ELSE
/// FOR i := 0 to 31
/// IF __eax[i]
/// ResetPredictionFeature(i)
/// FI
/// ENDFOR
/// FI
/// \endoperation
static __inline void __DEFAULT_FN_ATTRS
_hreset(int __eax)
{
__asm__ ("hreset $0" :: "a"(__eax));
}
#undef __DEFAULT_FN_ATTRS
#endif /* __has_extension(gnu_asm) */
#endif /* __HRESETINTRIN_H */

2
clang/lib/Headers/immintrin.h
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@ -10,6 +10,8 @@
#ifndef __IMMINTRIN_H
#define __IMMINTRIN_H
#include <x86gprintrin.h>
#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
defined(__MMX__)
#include <mmintrin.h>

18
clang/lib/Headers/x86gprintrin.h Normal file
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@ -0,0 +1,18 @@
/*===--------------- x86gprintrin.h - X86 GPR intrinsics ------------------===
*
* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
* See https://llvm.org/LICENSE.txt for license information.
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
*
*===-----------------------------------------------------------------------===
*/
#ifndef __X86GPRINTRIN_H
#define __X86GPRINTRIN_H
#if !(defined(_MSC_VER) || defined(__SCE__)) || __has_feature(modules) || \
defined(__HRESET__)
#include <hresetintrin.h>
#endif
#endif /* __X86GPRINTRIN_H */

11
clang/test/CodeGen/x86-hreset-intrin.c Normal file
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@ -0,0 +1,11 @@
// RUN: %clang_cc1 %s -ffreestanding -triple x86_64-unknown-unknown -target-feature +hreset -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 %s -ffreestanding -triple i386-unknown-unknown -target-feature +hreset -emit-llvm -o - | FileCheck %s
#include <immintrin.h>
void test_hreset(int a)
{
// CHECK-LABEL: test_hreset
// CHECK: call void asm sideeffect "hreset $$0", "{ax},~{dirflag},~{fpsr},~{flags}"(i32 %{{[0-9]}})
_hreset(a);
}

5
clang/test/Driver/x86-target-features.c
View File

@ -278,3 +278,8 @@
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-amx-int8 %s -### -o %t.o 2>&1 | FileCheck --check-prefix=NO-AMX-INT8 %s
// AMX-INT8: "-target-feature" "+amx-int8"
// NO-AMX-INT8: "-target-feature" "-amx-int8"
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mhreset %s -### -o %t.o 2>&1 | FileCheck -check-prefix=HRESET %s
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-hreset %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-HRESET %s
// HRESET: "-target-feature" "+hreset"
// NO-HRESET: "-target-feature" "-hreset"

8
clang/test/Preprocessor/x86_target_features.c
View File

@ -528,3 +528,11 @@
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-tsxldtrk -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOTSXLDTRK %s
// NOTSXLDTRK-NOT: #define __TSXLDTRK__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mhreset -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=HRESET %s
// HRESET: #define __HRESET__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-hreset -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOHRESET %s
// NOHRESET-NOT: #define __HRESET__ 1

1
llvm/docs/ReleaseNotes.rst
View File

@ -114,6 +114,7 @@ During this release ...
the "target-cpu" attribute or TargetMachine CPU which will be used to select
Instruction Set. If the attribute is not present, the tune CPU will follow
the target CPU.
* Support for ISA HRESET has been added.
Changes to the AMDGPU Target
-----------------------------

1
llvm/include/llvm/Support/X86TargetParser.def
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@ -187,6 +187,7 @@ X86_FEATURE (XSAVE, "xsave")
X86_FEATURE (XSAVEC, "xsavec")
X86_FEATURE (XSAVEOPT, "xsaveopt")
X86_FEATURE (XSAVES, "xsaves")
X86_FEATURE (HRESET, "hreset")
// These features aren't really CPU features, but the frontend can set them.
X86_FEATURE (RETPOLINE_EXTERNAL_THUNK, "retpoline-external-thunk")
X86_FEATURE (RETPOLINE_INDIRECT_BRANCHES, "retpoline-indirect-branches")

1
llvm/lib/Support/Host.cpp
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@ -1496,6 +1496,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
bool HasLeaf7Subleaf1 =
MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
Features["hreset"] = HasLeaf7Subleaf1 && ((EAX >> 22) & 1);
bool HasLeafD = MaxLevel >= 0xd &&
!getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);

1
llvm/lib/Support/X86TargetParser.cpp
View File

@ -558,6 +558,7 @@ constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4;
constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {};
constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE;
constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE;
constexpr FeatureBitset ImpliedFeaturesHRESET = {};
// Key Locker Features
constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2;

2
llvm/lib/Target/X86/X86.td
View File

@ -285,6 +285,8 @@ def FeatureKL : SubtargetFeature<"kl", "HasKL", "true",
def FeatureWIDEKL : SubtargetFeature<"widekl", "HasWIDEKL", "true",
"Support Key Locker wide Instructions",
[FeatureKL]>;
def FeatureHRESET : SubtargetFeature<"hreset", "HasHRESET", "true",
"Has hreset instruction">;
def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true",
"Has serialize instruction">;
def FeatureTSXLDTRK : SubtargetFeature<"tsxldtrk", "HasTSXLDTRK", "true",

1
llvm/lib/Target/X86/X86InstrFormats.td
View File

@ -216,6 +216,7 @@ class T8XS : T8 { Prefix OpPrefix = XS; }
class TAPS : TA { Prefix OpPrefix = PS; }
class TAPD : TA { Prefix OpPrefix = PD; }
class TAXD : TA { Prefix OpPrefix = XD; }
class TAXS : TA { Prefix OpPrefix = XS; }
class VEX { Encoding OpEnc = EncVEX; }
class VEX_W { bit HasVEX_W = 1; }
class VEX_WIG { bit IgnoresVEX_W = 1; }

8
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -972,6 +972,7 @@ def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">;
def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">;
def HasKL : Predicate<"Subtarget->hasKL()">;
def HasWIDEKL : Predicate<"Subtarget->hasWIDEKL()">;
def HasHRESET : Predicate<"Subtarget->hasHRESET()">;
def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
def HasTSXLDTRK : Predicate<"Subtarget->hasTSXLDTRK()">;
def HasAMXTILE : Predicate<"Subtarget->hasAMXTILE()">;
@ -2913,6 +2914,13 @@ let SchedRW = [WriteLoad] in {
def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>;
def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;
//===----------------------------------------------------------------------===//
// HRESET Instruction
//
let Uses = [EAX], SchedRW = [WriteSystem] in
def HRESET : Ii8<0xF0, MRM_C0, (outs), (ins i32u8imm:$imm), "hreset\t$imm", []>,
Requires<[HasHRESET]>, TAXS;
//===----------------------------------------------------------------------===//
// SERIALIZE Instruction
//

4
llvm/lib/Target/X86/X86Subtarget.h
View File

@ -401,6 +401,9 @@ class X86Subtarget final : public X86GenSubtargetInfo {
/// Processor support key locker wide instructions
bool HasWIDEKL = false;
/// Processor supports HRESET instruction
bool HasHRESET = false;
/// Processor supports SERIALIZE instruction
bool HasSERIALIZE = false;
@ -736,6 +739,7 @@ public:
bool hasENQCMD() const { return HasENQCMD; }
bool hasKL() const { return HasKL; }
bool hasWIDEKL() const { return HasWIDEKL; }
bool hasHRESET() const { return HasHRESET; }
bool hasSERIALIZE() const { return HasSERIALIZE; }
bool hasTSXLDTRK() const { return HasTSXLDTRK; }
bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }

3
llvm/test/MC/Disassembler/X86/x86-32.txt
View File

@ -1000,3 +1000,6 @@
#CHECK: tdcall
0x66 0x0f 0x01 0xcc
# CHECK: hreset $1
0xf3 0x0f 0x3a 0xf0 0xc0 0x01

3
llvm/test/MC/Disassembler/X86/x86-64.txt
View File

@ -712,3 +712,6 @@
#CHECK: tdcall
0x66 0x0f 0x01 0xcc
# CHECK: hreset $1
0xf3 0x0f 0x3a 0xf0 0xc0 0x01

6
llvm/test/MC/X86/x86-32-coverage.s
View File

@ -10891,4 +10891,8 @@ xresldtrk
// CHECK: tdcall
// CHECK: encoding: [0x66,0x0f,0x01,0xcc]
tdcall
tdcall
// CHECK: hreset
// CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
hreset $1

4
llvm/test/MC/X86/x86-64.s
View File

@ -2014,3 +2014,7 @@ seamops
// CHECK: tdcall
// CHECK: encoding: [0x66,0x0f,0x01,0xcc]
tdcall
// CHECK: hreset
// CHECK: encoding: [0xf3,0x0f,0x3a,0xf0,0xc0,0x01]
hreset $1