forked from OSchip/llvm-project
[SystemZ] Fix addcarry of addcarry of const carry (PR42606)
This fixes https://bugs.llvm.org/show_bug.cgi?id=42606 by extending D64213. Instead of only checking if the carry comes from a matching operation, we now check the full chain of carries. Otherwise we might custom lower the outermost addcarry, but then generically legalize an inner addcarry. Differential Revision: https://reviews.llvm.org/D64658 llvm-svn: 365949
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@ -3459,6 +3459,18 @@ SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
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return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
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}
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static bool isAddCarryChain(SDValue Carry) {
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while (Carry.getOpcode() == ISD::ADDCARRY)
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Carry = Carry.getOperand(2);
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return Carry.getOpcode() == ISD::UADDO;
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}
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static bool isSubBorrowChain(SDValue Carry) {
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while (Carry.getOpcode() == ISD::SUBCARRY)
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Carry = Carry.getOperand(2);
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return Carry.getOpcode() == ISD::USUBO;
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}
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// Lower ADDCARRY/SUBCARRY nodes.
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SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
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SelectionDAG &DAG) const {
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@ -3481,7 +3493,7 @@ SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
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switch (Op.getOpcode()) {
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default: llvm_unreachable("Unknown instruction!");
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case ISD::ADDCARRY:
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if (Carry.getOpcode() != ISD::UADDO && Carry.getOpcode() != ISD::ADDCARRY)
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if (!isAddCarryChain(Carry))
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return SDValue();
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BaseOp = SystemZISD::ADDCARRY;
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@ -3489,7 +3501,7 @@ SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
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CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
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break;
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case ISD::SUBCARRY:
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if (Carry.getOpcode() != ISD::USUBO && Carry.getOpcode() != ISD::SUBCARRY)
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if (!isSubBorrowChain(Carry))
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return SDValue();
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BaseOp = SystemZISD::SUBCARRY;
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@ -0,0 +1,35 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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define i64 @test(i64 %lo, i64 %hi) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0:
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; CHECK-NEXT: la %r0, 0(%r2,%r2)
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; CHECK-NEXT: clgr %r0, %r2
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; CHECK-NEXT: ipm %r0
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; CHECK-NEXT: la %r1, 1(%r2,%r2)
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; CHECK-NEXT: cghi %r1, 0
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: afi %r1, -268435456
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; CHECK-NEXT: srl %r1, 31
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; CHECK-NEXT: rosbg %r1, %r0, 63, 63, 36
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; CHECK-NEXT: algfr %r3, %r1
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; CHECK-NEXT: lgr %r2, %r3
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; CHECK-NEXT: br %r14
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%tmp = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %lo, i64 1)
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%tmp1 = extractvalue { i64, i1 } %tmp, 0
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%tmp2 = extractvalue { i64, i1 } %tmp, 1
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%tmp3 = zext i1 %tmp2 to i64
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%tmp4 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %lo, i64 %tmp1)
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%tmp5 = extractvalue { i64, i1 } %tmp4, 1
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%tmp6 = zext i1 %tmp5 to i64
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%spec.select.i = add i64 0, %hi
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%tmp7 = add i64 %spec.select.i, %tmp3
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%tmp8 = add i64 %tmp7, %tmp6
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ret i64 %tmp8
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}
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; Function Attrs: nounwind readnone speculatable
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declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) #0
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attributes #0 = { nounwind readnone speculatable }
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