[SystemZ] Fix addcarry of addcarry of const carry (PR42606)

This fixes https://bugs.llvm.org/show_bug.cgi?id=42606 by extending
D64213. Instead of only checking if the carry comes from a matching
operation, we now check the full chain of carries. Otherwise we might
custom lower the outermost addcarry, but then generically legalize
an inner addcarry.

Differential Revision: https://reviews.llvm.org/D64658

llvm-svn: 365949
This commit is contained in:
Nikita Popov 2019-07-12 20:03:34 +00:00
parent f561227d13
commit 411fa4c0df
2 changed files with 49 additions and 2 deletions

View File

@ -3459,6 +3459,18 @@ SDValue SystemZTargetLowering::lowerXALUO(SDValue Op,
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, SetCC);
}
static bool isAddCarryChain(SDValue Carry) {
while (Carry.getOpcode() == ISD::ADDCARRY)
Carry = Carry.getOperand(2);
return Carry.getOpcode() == ISD::UADDO;
}
static bool isSubBorrowChain(SDValue Carry) {
while (Carry.getOpcode() == ISD::SUBCARRY)
Carry = Carry.getOperand(2);
return Carry.getOpcode() == ISD::USUBO;
}
// Lower ADDCARRY/SUBCARRY nodes.
SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
SelectionDAG &DAG) const {
@ -3481,7 +3493,7 @@ SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
switch (Op.getOpcode()) {
default: llvm_unreachable("Unknown instruction!");
case ISD::ADDCARRY:
if (Carry.getOpcode() != ISD::UADDO && Carry.getOpcode() != ISD::ADDCARRY)
if (!isAddCarryChain(Carry))
return SDValue();
BaseOp = SystemZISD::ADDCARRY;
@ -3489,7 +3501,7 @@ SDValue SystemZTargetLowering::lowerADDSUBCARRY(SDValue Op,
CCMask = SystemZ::CCMASK_LOGICAL_CARRY;
break;
case ISD::SUBCARRY:
if (Carry.getOpcode() != ISD::USUBO && Carry.getOpcode() != ISD::SUBCARRY)
if (!isSubBorrowChain(Carry))
return SDValue();
BaseOp = SystemZISD::SUBCARRY;

View File

@ -0,0 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @test(i64 %lo, i64 %hi) {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: la %r0, 0(%r2,%r2)
; CHECK-NEXT: clgr %r0, %r2
; CHECK-NEXT: ipm %r0
; CHECK-NEXT: la %r1, 1(%r2,%r2)
; CHECK-NEXT: cghi %r1, 0
; CHECK-NEXT: ipm %r1
; CHECK-NEXT: afi %r1, -268435456
; CHECK-NEXT: srl %r1, 31
; CHECK-NEXT: rosbg %r1, %r0, 63, 63, 36
; CHECK-NEXT: algfr %r3, %r1
; CHECK-NEXT: lgr %r2, %r3
; CHECK-NEXT: br %r14
%tmp = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %lo, i64 1)
%tmp1 = extractvalue { i64, i1 } %tmp, 0
%tmp2 = extractvalue { i64, i1 } %tmp, 1
%tmp3 = zext i1 %tmp2 to i64
%tmp4 = tail call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %lo, i64 %tmp1)
%tmp5 = extractvalue { i64, i1 } %tmp4, 1
%tmp6 = zext i1 %tmp5 to i64
%spec.select.i = add i64 0, %hi
%tmp7 = add i64 %spec.select.i, %tmp3
%tmp8 = add i64 %tmp7, %tmp6
ret i64 %tmp8
}
; Function Attrs: nounwind readnone speculatable
declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) #0
attributes #0 = { nounwind readnone speculatable }