forked from OSchip/llvm-project
[X86] Qualify a few places with ExperimentalVectorWideningLegalization.
I'm playing around with this flag and these places cause errors if not qualified. llvm-svn: 318595
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@ -24602,8 +24602,10 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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SDValue InVec1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, RegVT, Ops);
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SDValue Res = DAG.getNode(X86ISD::AVG, dl, RegVT, InVec0, InVec1);
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Results.push_back(DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
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DAG.getIntPtrConstant(0, dl)));
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if (!ExperimentalVectorWideningLegalization)
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Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InVT, Res,
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DAG.getIntPtrConstant(0, dl));
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Results.push_back(Res);
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return;
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}
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// We might have generated v2f32 FMIN/FMAX operations. Widen them to v4f32.
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@ -24645,6 +24647,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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SDValue Res = DAG.getNode(IsSigned ? X86ISD::CVTTP2SI
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: X86ISD::CVTTP2UI,
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dl, MVT::v4i32, Src);
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if (!ExperimentalVectorWideningLegalization)
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Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, Idx);
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Results.push_back(Res);
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return;
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@ -24655,6 +24658,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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DAG.getUNDEF(MVT::v2f32));
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Res = DAG.getNode(IsSigned ? ISD::FP_TO_SINT
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: ISD::FP_TO_UINT, dl, MVT::v4i32, Res);
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if (!ExperimentalVectorWideningLegalization)
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Res = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v2i32, Res, Idx);
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Results.push_back(Res);
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return;
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