forked from OSchip/llvm-project
Support inline asm with multiple 64bit output in 32bit GPR
Summary: Extend fix for PR34170 to support inline assembly with multiple output operands that do not naturally go in the register class it is constrained to (eg. double in a 32-bit GPR as in the PR). Reviewers: bogner, t.p.northover, lattner, javed.absar, efriedma Reviewed By: efriedma Subscribers: efriedma, tra, eraman, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D45437 llvm-svn: 339225
This commit is contained in:
Thomas Preud'homme
parent
2f84d91131
commit
4107b31df2
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@ -7776,10 +7776,29 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
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SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(),
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Chain, &Flag, CS.getInstruction());
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// FIXME: Why don't we do this for inline asms with MRVs?
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if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
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EVT ResultType = TLI.getValueType(DAG.getDataLayout(), CS.getType());
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llvm::Type *CSResultType = CS.getType();
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unsigned numRet;
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ArrayRef<Type *> ResultTypes;
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SmallVector<SDValue, 1> ResultValues(1);
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if (CSResultType->isSingleValueType()) {
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numRet = 1;
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ResultValues[0] = Val;
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ResultTypes = makeArrayRef(CSResultType);
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} else {
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numRet = CSResultType->getNumContainedTypes();
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assert(Val->getNumOperands() == numRet &&
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"Mismatch in number of output operands in asm result");
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ResultTypes = CSResultType->subtypes();
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ArrayRef<SDUse> ValueUses = Val->ops();
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ResultValues.resize(numRet);
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std::transform(ValueUses.begin(), ValueUses.end(), ResultValues.begin(),
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[](const SDUse &u) -> SDValue { return u.get(); });
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}
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SmallVector<EVT, 1> ResultVTs(numRet);
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for (unsigned i = 0; i < numRet; i++) {
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EVT ResultVT = TLI.getValueType(DAG.getDataLayout(), ResultTypes[i]);
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SDValue Val = ResultValues[i];
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assert(ResultTypes[i]->isSized() && "Unexpected unsized type");
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// If the type of the inline asm call site return value is different but
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// has same size as the type of the asm output bitcast it. One example
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// of this is for vectors with different width / number of elements.
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@ -7790,22 +7809,24 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
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// This can also happen for a return value that disagrees with the
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// register class it is put in, eg. a double in a general-purpose
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// register on a 32-bit machine.
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if (ResultType != Val.getValueType() &&
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ResultType.getSizeInBits() == Val.getValueSizeInBits()) {
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Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(),
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ResultType, Val);
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} else if (ResultType != Val.getValueType() &&
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ResultType.isInteger() && Val.getValueType().isInteger()) {
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// If a result value was tied to an input value, the computed result may
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// have a wider width than the expected result. Extract the relevant
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// portion.
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Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultType, Val);
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if (ResultVT != Val.getValueType() &&
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ResultVT.getSizeInBits() == Val.getValueSizeInBits())
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Val = DAG.getNode(ISD::BITCAST, getCurSDLoc(), ResultVT, Val);
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else if (ResultVT != Val.getValueType() && ResultVT.isInteger() &&
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Val.getValueType().isInteger()) {
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// If a result value was tied to an input value, the computed result
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// may have a wider width than the expected result. Extract the
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// relevant portion.
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Val = DAG.getNode(ISD::TRUNCATE, getCurSDLoc(), ResultVT, Val);
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}
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assert(ResultType == Val.getValueType() && "Asm result value mismatch!");
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assert(ResultVT == Val.getValueType() && "Asm result value mismatch!");
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ResultVTs[i] = ResultVT;
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ResultValues[i] = Val;
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}
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Val = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(),
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DAG.getVTList(ResultVTs), ResultValues);
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setValue(CS.getInstruction(), Val);
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// Don't need to use this as a chain in this case.
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if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty())
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@ -1,122 +0,0 @@
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; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 < %s | FileCheck %s
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; Check support for returning a float in GPR with soft float ABI
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define arm_aapcscc float @zerobits_float_soft() #0 {
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; CHECK-LABEL: zerobits_float_soft
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; CHECK: mov r0, #0
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%1 = tail call float asm "mov ${0}, #0", "=&r"()
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ret float %1
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}
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; Check support for returning a double in GPR with soft float ABI
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define arm_aapcscc double @zerobits_double_soft() #0 {
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; CHECK-LABEL: zerobits_double_soft
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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%1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"()
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ret double %1
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}
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; Check support for returning a float in GPR with matching float input with
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; soft float ABI
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define arm_aapcscc float @flt_gpr_matching_in_op_soft(float %f) #0 {
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; CHECK-LABEL: flt_gpr_matching_in_op_soft
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; CHECK: mov r0, r0
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%1 = call float asm "mov $0, $1", "=&r,0"(float %f)
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ret float %1
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}
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; Check support for returning a double in GPR with matching double input with
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; soft float ABI
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define arm_aapcscc double @dbl_gpr_matching_in_op_soft(double %d) #0 {
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; CHECK-LABEL: dbl_gpr_matching_in_op_soft
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; CHECK: mov r1, r0
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
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ret double %1
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}
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; Check support for returning a float in specific GPR with matching float input
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; with soft float ABI
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define arm_aapcscc float @flt_gpr_matching_spec_reg_in_op_soft(float %f) #0 {
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; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r3
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%1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)
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ret float %1
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}
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; Check support for returning a double in specific GPR with matching double
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; input with soft float ABI
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define arm_aapcscc double @dbl_gpr_matching_spec_reg_in_op_soft(double %d) #0 {
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; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r2
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)
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ret double %1
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}
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attributes #0 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="true" }
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; Check support for returning a float in GPR with hard float ABI
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define float @zerobits_float_hard() #1 {
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; CHECK-LABEL: zerobits_float_hard
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; CHECK: mov r0, #0
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; CHECK: vmov s0, r0
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%1 = tail call float asm "mov ${0}, #0", "=&r"()
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ret float %1
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}
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; Check support for returning a double in GPR with hard float ABI
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define double @zerobits_double_hard() #1 {
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; CHECK-LABEL: zerobits_double_hard
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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; CHECK: vmov d0, r0, r1
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%1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"()
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ret double %1
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}
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; Check support for returning a float in GPR with matching float input with
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; hard float ABI
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define float @flt_gpr_matching_in_op_hard(float %f) #1 {
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; CHECK-LABEL: flt_gpr_matching_in_op_hard
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; CHECK: vmov r0, s0
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; CHECK: mov r0, r0
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; CHECK: vmov s0, r0
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%1 = call float asm "mov $0, $1", "=&r,0"(float %f)
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ret float %1
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}
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; Check support for returning a double in GPR with matching double input with
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; hard float ABI
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define double @dbl_gpr_matching_in_op_hard(double %d) #1 {
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; CHECK-LABEL: dbl_gpr_matching_in_op_hard
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; CHECK: vmov r0, r1, d0
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; CHECK: mov r1, r0
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; CHECK: vmov d0, r0, r1
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
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ret double %1
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}
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; Check support for returning a float in specific GPR with matching float
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; input with hard float ABI
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define float @flt_gpr_matching_spec_reg_in_op_hard(float %f) #1 {
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; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_hard
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; CHECK: vmov r3, s0
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; CHECK: mov r3, r3
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; CHECK: vmov s0, r3
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%1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)
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ret float %1
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}
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; Check support for returning a double in specific GPR with matching double
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; input with hard float ABI
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define double @dbl_gpr_matching_spec_reg_in_op_hard(double %d) #1 {
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; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_hard
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; CHECK: vmov r2, r3, d0
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; CHECK: mov r3, r2
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; CHECK: vmov d0, r2, r3
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)
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ret double %1
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}
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attributes #1 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="false" }
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@ -0,0 +1,307 @@
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; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 < %s | FileCheck %s
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%struct.twofloat = type { float, float }
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%struct.twodouble = type { double, double }
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; Check support for returning a float in GPR with soft float ABI
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define arm_aapcscc float @zerobits_float_soft() #0 {
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; CHECK-LABEL: zerobits_float_soft
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; CHECK: mov r0, #0
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%1 = tail call float asm "mov ${0}, #0", "=&r"()
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ret float %1
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}
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; Check support for returning a double in GPR with soft float ABI
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define arm_aapcscc double @zerobits_double_soft() #0 {
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; CHECK-LABEL: zerobits_double_soft
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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%1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"()
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ret double %1
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}
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; Check support for returning a float in GPR with matching float input with
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; soft float ABI
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define arm_aapcscc float @flt_gpr_matching_in_op_soft(float %f) #0 {
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; CHECK-LABEL: flt_gpr_matching_in_op_soft
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; CHECK: mov r0, r0
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%1 = call float asm "mov $0, $1", "=&r,0"(float %f)
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ret float %1
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}
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; Check support for returning a double in GPR with matching double input with
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; soft float ABI
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define arm_aapcscc double @dbl_gpr_matching_in_op_soft(double %d) #0 {
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; CHECK-LABEL: dbl_gpr_matching_in_op_soft
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; CHECK: mov r1, r0
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
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ret double %1
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}
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; Check support for returning a float in specific GPR with matching float input
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; with soft float ABI
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define arm_aapcscc float @flt_gpr_matching_spec_reg_in_op_soft(float %f) #0 {
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; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r3
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%1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)
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ret float %1
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}
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; Check support for returning a double in specific GPR with matching double
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; input with soft float ABI
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define arm_aapcscc double @dbl_gpr_matching_spec_reg_in_op_soft(double %d) #0 {
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; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r2
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%1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)
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ret double %1
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}
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; Check support for returning several float in GPR
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define arm_aapcscc float @zerobits_float_convoluted_soft() #0 {
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; CHECK-LABEL: zerobits_float_convoluted_soft
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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%1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"()
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%asmresult = extractvalue { float, float } %1, 0
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%asmresult1 = extractvalue { float, float } %1, 1
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%add = fadd float %asmresult, %asmresult1
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ret float %add
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}
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; Check support for returning several double in GPR
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define double @zerobits_double_convoluted_soft() #0 {
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; CHECK-LABEL: zerobits_double_convoluted_soft
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: mov r3, #0
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%1 = call { double, double } asm "mov ${0:Q}, #0; mov ${0:R}, #0; mov ${1:Q}, #0; mov ${1:R}, #0", "=r,=r"()
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%asmresult = extractvalue { double, double } %1, 0
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%asmresult1 = extractvalue { double, double } %1, 1
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%add = fadd double %asmresult, %asmresult1
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ret double %add
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}
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; Check support for returning several floats in GPRs with matching float inputs
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; with soft float ABI
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define arm_aapcscc float @flt_gprs_matching_in_op_soft(float %f1, float %f2) #0 {
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; CHECK-LABEL: flt_gprs_matching_in_op_soft
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; CHECK: mov r0, r0
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; CHECK-NEXT: mov r1, r1
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%1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&r,=&r,0,1"(float %f1, float %f2)
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%asmresult1 = extractvalue { float, float } %1, 0
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%asmresult2 = extractvalue { float, float } %1, 1
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%add = fadd float %asmresult1, %asmresult2
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ret float %add
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}
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; Check support for returning several double in GPRs with matching double input
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; with soft float ABI
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define arm_aapcscc double @dbl_gprs_matching_in_op_soft(double %d1, double %d2) #0 {
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; CHECK-LABEL: dbl_gprs_matching_in_op_soft
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; CHECK: mov r1, r0
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; CHECK-NEXT: mov r3, r2
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%1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&r,=&r,0,1"(double %d1, double %d2)
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%asmresult1 = extractvalue { double, double } %1, 0
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%asmresult2 = extractvalue { double, double } %1, 1
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%add = fadd double %asmresult1, %asmresult2
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ret double %add
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}
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; Check support for returning several float in specific GPRs with matching
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; float input with soft float ABI
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define arm_aapcscc float @flt_gprs_matching_spec_reg_in_op_soft(float %f1, float %f2) #0 {
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; CHECK-LABEL: flt_gprs_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r3
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; CHECK-NEXT: mov r4, r4
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%1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&{r3},=&{r4},0,1"(float %f1, float %f2)
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%asmresult1 = extractvalue { float, float } %1, 0
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%asmresult2 = extractvalue { float, float } %1, 1
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%add = fadd float %asmresult1, %asmresult2
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ret float %add
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}
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; Check support for returning several double in specific GPRs with matching
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; double input with soft float ABI
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define arm_aapcscc double @dbl_gprs_matching_spec_reg_in_op_soft(double %d1, double %d2) #0 {
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; CHECK-LABEL: dbl_gprs_matching_spec_reg_in_op_soft
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; CHECK: mov r3, r2
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; CHECK-NEXT: mov r5, r4
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%1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&{r2},=&{r4},0,1"(double %d1, double %d2)
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%asmresult1 = extractvalue { double, double } %1, 0
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%asmresult2 = extractvalue { double, double } %1, 1
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%add = fadd double %asmresult1, %asmresult2
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ret double %add
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}
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attributes #0 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="true" }
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; Check support for returning a float in GPR with hard float ABI
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define float @zerobits_float_hard() #1 {
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; CHECK-LABEL: zerobits_float_hard
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; CHECK: mov r0, #0
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; CHECK: vmov s0, r0
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%1 = tail call float asm "mov ${0}, #0", "=&r"()
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ret float %1
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}
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; Check support for returning a double in GPR with hard float ABI
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define double @zerobits_double_hard() #1 {
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; CHECK-LABEL: zerobits_double_hard
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; CHECK: mov r0, #0
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; CHECK-NEXT: mov r1, #0
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; CHECK: vmov d0, r0, r1
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%1 = tail call double asm "mov ${0:Q}, #0\0Amov ${0:R}, #0", "=&r"()
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ret double %1
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}
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; Check support for returning a float in GPR with matching float input with
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; hard float ABI
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define float @flt_gpr_matching_in_op_hard(float %f) #1 {
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; CHECK-LABEL: flt_gpr_matching_in_op_hard
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; CHECK: vmov r0, s0
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; CHECK: mov r0, r0
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; CHECK: vmov s0, r0
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%1 = call float asm "mov $0, $1", "=&r,0"(float %f)
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ret float %1
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}
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; Check support for returning a double in GPR with matching double input with
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; hard float ABI
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define double @dbl_gpr_matching_in_op_hard(double %d) #1 {
|
||||
; CHECK-LABEL: dbl_gpr_matching_in_op_hard
|
||||
; CHECK: vmov r0, r1, d0
|
||||
; CHECK: mov r1, r0
|
||||
; CHECK: vmov d0, r0, r1
|
||||
%1 = call double asm "mov ${0:R}, ${1:Q}", "=&r,0"(double %d)
|
||||
ret double %1
|
||||
}
|
||||
|
||||
; Check support for returning a float in specific GPR with matching float
|
||||
; input with hard float ABI
|
||||
define float @flt_gpr_matching_spec_reg_in_op_hard(float %f) #1 {
|
||||
; CHECK-LABEL: flt_gpr_matching_spec_reg_in_op_hard
|
||||
; CHECK: vmov r3, s0
|
||||
; CHECK: mov r3, r3
|
||||
; CHECK: vmov s0, r3
|
||||
%1 = call float asm "mov $0, $1", "=&{r3},0"(float %f)
|
||||
ret float %1
|
||||
}
|
||||
|
||||
; Check support for returning a double in specific GPR with matching double
|
||||
; input with hard float ABI
|
||||
define double @dbl_gpr_matching_spec_reg_in_op_hard(double %d) #1 {
|
||||
; CHECK-LABEL: dbl_gpr_matching_spec_reg_in_op_hard
|
||||
; CHECK: vmov r2, r3, d0
|
||||
; CHECK: mov r3, r2
|
||||
; CHECK: vmov d0, r2, r3
|
||||
%1 = call double asm "mov ${0:R}, ${1:Q}", "=&{r2},0"(double %d)
|
||||
ret double %1
|
||||
}
|
||||
|
||||
; Check support for returning several float in GPR
|
||||
define %struct.twofloat @zerobits_float_convoluted_hard() #1 {
|
||||
; CHECK-LABEL: zerobits_float_convoluted_hard
|
||||
; CHECK: mov r0, #0
|
||||
; CHECK-NEXT: mov r1, #0
|
||||
; CHECK: vmov s0, r0
|
||||
; CHECK-NEXT: vmov s1, r1
|
||||
%1 = call { float, float } asm "mov $0, #0; mov $1, #0", "=r,=r"()
|
||||
%asmresult1 = extractvalue { float, float } %1, 0
|
||||
%asmresult2 = extractvalue { float, float } %1, 1
|
||||
%partialres = insertvalue %struct.twofloat undef, float %asmresult1, 0
|
||||
%res = insertvalue %struct.twofloat %partialres, float %asmresult2, 1
|
||||
ret %struct.twofloat %res
|
||||
}
|
||||
|
||||
; Check support for returning several double in GPR
|
||||
define %struct.twodouble @zerobits_double_convoluted_hard() #1 {
|
||||
; CHECK-LABEL: zerobits_double_convoluted_hard
|
||||
; CHECK: mov r0, #0
|
||||
; CHECK-NEXT: mov r1, #0
|
||||
; CHECK-NEXT: mov r2, #0
|
||||
; CHECK-NEXT: mov r3, #0
|
||||
; CHECK: vmov d0, r0, r1
|
||||
; CHECK-NEXT: vmov d1, r2, r3
|
||||
%1 = call { double, double } asm "mov ${0:Q}, #0; mov ${0:R}, #0; mov ${1:Q}, #0; mov ${1:R}, #0", "=r,=r"()
|
||||
%asmresult1 = extractvalue { double, double } %1, 0
|
||||
%asmresult2 = extractvalue { double, double } %1, 1
|
||||
%partialres = insertvalue %struct.twodouble undef, double %asmresult1, 0
|
||||
%res = insertvalue %struct.twodouble %partialres, double %asmresult2, 1
|
||||
ret %struct.twodouble %res
|
||||
}
|
||||
|
||||
; Check support for returning several floats in GPRs with matching float inputs
|
||||
; with hard float ABI
|
||||
define %struct.twofloat @flt_gprs_matching_in_op_hard(float %f1, float %f2) #1 {
|
||||
; CHECK-LABEL: flt_gprs_matching_in_op_hard
|
||||
; CHECK: vmov r0, s0
|
||||
; CHECK-NEXT: vmov r1, s1
|
||||
; CHECK: mov r0, r0
|
||||
; CHECK-NEXT: mov r1, r1
|
||||
; CHECK: vmov s0, r0
|
||||
; CHECK-NEXT: vmov s1, r1
|
||||
%1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&r,=&r,0,1"(float %f1, float %f2)
|
||||
%asmresult1 = extractvalue { float, float } %1, 0
|
||||
%asmresult2 = extractvalue { float, float } %1, 1
|
||||
%partialres = insertvalue %struct.twofloat undef, float %asmresult1, 0
|
||||
%res = insertvalue %struct.twofloat %partialres, float %asmresult2, 1
|
||||
ret %struct.twofloat %res
|
||||
}
|
||||
|
||||
; Check support for returning several double in GPRs with matching double input
|
||||
; with hard float ABI
|
||||
define %struct.twodouble @dbl_gprs_matching_in_op_hard(double %d1, double %d2) #1 {
|
||||
; CHECK-LABEL: dbl_gprs_matching_in_op_hard
|
||||
; CHECK: vmov r0, r1, d0
|
||||
; CHECK-NEXT: vmov r2, r3, d1
|
||||
; CHECK: mov r1, r0
|
||||
; CHECK-NEXT: mov r3, r2
|
||||
; CHECK: vmov d0, r0, r1
|
||||
; CHECK-NEXT: vmov d1, r2, r3
|
||||
%1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&r,=&r,0,1"(double %d1, double %d2)
|
||||
%asmresult1 = extractvalue { double, double } %1, 0
|
||||
%asmresult2 = extractvalue { double, double } %1, 1
|
||||
%partialres = insertvalue %struct.twodouble undef, double %asmresult1, 0
|
||||
%res = insertvalue %struct.twodouble %partialres, double %asmresult2, 1
|
||||
ret %struct.twodouble %res
|
||||
}
|
||||
|
||||
; Check support for returning several float in specific GPRs with matching
|
||||
; float input with hard float ABI
|
||||
define %struct.twofloat @flt_gprs_matching_spec_reg_in_op_hard(float %f1, float %f2) #1 {
|
||||
; CHECK-LABEL: flt_gprs_matching_spec_reg_in_op_hard
|
||||
; CHECK: vmov r3, s0
|
||||
; CHECK-NEXT: vmov r4, s1
|
||||
; CHECK: mov r3, r3
|
||||
; CHECK-NEXT: mov r4, r4
|
||||
; CHECK: vmov s0, r3
|
||||
; CHECK-NEXT: vmov s1, r4
|
||||
%1 = call { float, float } asm "mov $0, $2; mov $1, $3", "=&{r3},=&{r4},0,1"(float %f1, float %f2)
|
||||
%asmresult1 = extractvalue { float, float } %1, 0
|
||||
%asmresult2 = extractvalue { float, float } %1, 1
|
||||
%partialres = insertvalue %struct.twofloat undef, float %asmresult1, 0
|
||||
%res = insertvalue %struct.twofloat %partialres, float %asmresult2, 1
|
||||
ret %struct.twofloat %res
|
||||
}
|
||||
|
||||
; Check support for returning several double in specific GPRs with matching
|
||||
; double input with hard float ABI
|
||||
define %struct.twodouble @dbl_gprs_matching_spec_reg_in_op_hard(double %d1, double %d2) #1 {
|
||||
; CHECK-LABEL: dbl_gprs_matching_spec_reg_in_op_hard
|
||||
; CHECK: vmov r2, r3, d0
|
||||
; CHECK-NEXT: vmov r4, r5, d1
|
||||
; CHECK: mov r3, r2
|
||||
; CHECK-NEXT: mov r5, r4
|
||||
; CHECK: vmov d0, r2, r3
|
||||
; CHECK-NEXT: vmov d1, r4, r5
|
||||
%1 = call { double, double } asm "mov ${0:R}, ${2:Q}; mov ${1:R}, ${3:Q}", "=&{r2},=&{r4},0,1"(double %d1, double %d2)
|
||||
%asmresult1 = extractvalue { double, double } %1, 0
|
||||
%asmresult2 = extractvalue { double, double } %1, 1
|
||||
%partialres = insertvalue %struct.twodouble undef, double %asmresult1, 0
|
||||
%res = insertvalue %struct.twodouble %partialres, double %asmresult2, 1
|
||||
ret %struct.twodouble %res
|
||||
}
|
||||
|
||||
attributes #1 = { nounwind "target-features"="+d16,+vfp2,+vfp3,-fp-only-sp" "use-soft-float"="false" }
|
||||
Loading…
Reference in New Issue