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Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases 

should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.

llvm-svn: 104883
This commit is contained in:
Bob Wilson 2010-05-27 20:23:42 +00:00
parent ab366f055a
commit 40e62dfdc0
1 changed files with 18 additions and 12 deletions
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30
llvm/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
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@ -1064,21 +1064,27 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
printOperand(MI, OpNum, O);
return false;
case 'Q':
if (TM.getTargetData()->isLittleEndian())
break;
// Fallthrough
case 'R':
// Print the least significant half of a register pair.
if (TM.getTargetData()->isBigEndian())
break;
// Fallthrough
case 'H': // Write second word of DI / DF reference.
// Verify that this operand has two consecutive registers.
if (!MI->getOperand(OpNum).isReg() ||
OpNum+1 == MI->getNumOperands() ||
!MI->getOperand(OpNum+1).isReg())
return true;
++OpNum; // Return the high-part.
printOperand(MI, OpNum, O);
return false;
case 'R':
// Print the most significant half of a register pair.
if (TM.getTargetData()->isLittleEndian())
break;
printOperand(MI, OpNum, O);
return false;
case 'H':
break;
}
// Print the second half of a register pair (for 'Q', 'R' or 'H').
// Verify that this operand has two consecutive registers.
if (!MI->getOperand(OpNum).isReg() ||
OpNum+1 == MI->getNumOperands() ||
!MI->getOperand(OpNum+1).isReg())
return true;
++OpNum;
}
printOperand(MI, OpNum, O);