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[X86] Add RAX/EAX/AX Uses/Defs to XCHG RAX/EAX/AX instructions. 

llvm-svn: 202347
This commit is contained in:
Craig Topper 2014-02-27 04:27:00 +00:00
parent 1b7ed91e44
commit 40dd6211d5
1 changed files with 4 additions and 0 deletions
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4
llvm/lib/Target/X86/X86InstrInfo.td
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@ -1684,16 +1684,20 @@ def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
} }
// Swap between EAX and other registers. // Swap between EAX and other registers.
let Uses = [AX], Defs = [AX] in
def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src), def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
"xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16; "xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
let Uses = [EAX], Defs = [EAX] in
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src), def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
"xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
OpSize32, Requires<[Not64BitMode]>; OpSize32, Requires<[Not64BitMode]>;
let Uses = [EAX], Defs = [EAX] in
// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding. // Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP. // xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src), def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
"xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>, "xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
OpSize32, Requires<[In64BitMode]>; OpSize32, Requires<[In64BitMode]>;
let Uses = [RAX], Defs = [RAX] in
def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src), def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
"xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>; "xchg{q}\t{$src, %rax|rax, $src}", [], IIC_XCHG_REG>;
} // SchedRW } // SchedRW