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Use __func__ directly now that all supported compilers support it 

Remove the portability macro now that it is unused.

llvm-svn: 284681
This commit is contained in:
Reid Kleckner 2016-10-20 00:22:23 +00:00
parent 2918d0b4b2
commit 40d7230f2f
7 changed files with 11 additions and 20 deletions
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9
llvm/include/llvm/Support/Compiler.h
View File

@ -383,15 +383,6 @@
# define LLVM_PTR_SIZE sizeof(void *)
#endif
/// \macro LLVM_FUNCTION_NAME
/// \brief Expands to __func__ on compilers which support it. Otherwise,
/// expands to a compiler-dependent replacement.
#if defined(_MSC_VER)
# define LLVM_FUNCTION_NAME __FUNCTION__
#else
# define LLVM_FUNCTION_NAME __func__
#endif
/// \macro LLVM_MEMORY_SANITIZER_BUILD
/// \brief Whether LLVM itself is built with MemorySanitizer instrumentation.
#if __has_feature(memory_sanitizer)

6
llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
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@ -383,9 +383,9 @@ void HexagonBlockRanges::computeInitialLiveRanges(InstrIndexMap &IndexMap,
HexagonBlockRanges::RegToRangeMap HexagonBlockRanges::computeLiveMap(
InstrIndexMap &IndexMap) {
RegToRangeMap LiveMap;
DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": index map\n" << IndexMap << '\n');
DEBUG(dbgs() << __func__ << ": index map\n" << IndexMap << '\n');
computeInitialLiveRanges(IndexMap, LiveMap);
DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": live map\n"
DEBUG(dbgs() << __func__ << ": live map\n"
<< PrintRangeMap(LiveMap, TRI) << '\n');
return LiveMap;
}
@ -448,7 +448,7 @@ HexagonBlockRanges::RegToRangeMap HexagonBlockRanges::computeDeadMap(
if (TargetRegisterInfo::isVirtualRegister(P.first.Reg))
addDeadRanges(P.first);
DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": dead map\n"
DEBUG(dbgs() << __func__ << ": dead map\n"
<< PrintRangeMap(DeadMap, TRI) << '\n');
return DeadMap;
}

2
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
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@ -1315,7 +1315,7 @@ static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
bool HexagonFrameLowering::assignCalleeSavedSpillSlots(MachineFunction &MF,
const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
DEBUG(dbgs() << LLVM_FUNCTION_NAME << " on "
DEBUG(dbgs() << __func__ << " on "
<< MF.getFunction()->getName() << '\n');
MachineFrameInfo &MFI = MF.getFrameInfo();
BitVector SRegs(Hexagon::NUM_TARGET_REGS);

2
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
View File

@ -757,7 +757,7 @@ unsigned HexagonGenInsert::distance(MachineBasicBlock::const_iterator FromI,
bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
OrderedRegisterList &AVs) {
if (isDebug()) {
dbgs() << LLVM_FUNCTION_NAME << ": " << PrintReg(VR, HRI)
dbgs() << __func__ << ": " << PrintReg(VR, HRI)
<< " AVs: " << PrintORL(AVs, HRI) << "\n";
}
if (AVs.size() == 0)

8
llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
View File

@ -202,7 +202,7 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) {
void HexagonGenPredicate::processPredicateGPR(const Register &Reg) {
DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": "
DEBUG(dbgs() << __func__ << ": "
<< PrintReg(Reg.R, TRI, Reg.S) << "\n");
typedef MachineRegisterInfo::use_iterator use_iterator;
use_iterator I = MRI->use_begin(Reg.R), E = MRI->use_end();
@ -230,7 +230,7 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) {
if (F != G2P.end())
return F->second;
DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << PrintRegister(Reg, *TRI));
DEBUG(dbgs() << __func__ << ": " << PrintRegister(Reg, *TRI));
MachineInstr *DefI = MRI->getVRegDef(Reg.R);
assert(DefI);
unsigned Opc = DefI->getOpcode();
@ -346,7 +346,7 @@ bool HexagonGenPredicate::isScalarPred(Register PredReg) {
bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << MI << " " << *MI);
DEBUG(dbgs() << __func__ << ": " << MI << " " << *MI);
unsigned Opc = MI->getOpcode();
assert(isConvertibleToPredForm(MI));
@ -432,7 +432,7 @@ bool HexagonGenPredicate::convertToPredForm(MachineInstr *MI) {
bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
DEBUG(dbgs() << LLVM_FUNCTION_NAME << "\n");
DEBUG(dbgs() << __func__ << "\n");
const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
bool Changed = false;
VectOfInst Erase;

2
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -1067,7 +1067,7 @@ HexagonTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
A = HFI.getStackAlignment();
DEBUG({
dbgs () << LLVM_FUNCTION_NAME << " Align: " << A << " Size: ";
dbgs () << __func__ << " Align: " << A << " Size: ";
Size.getNode()->dump(&DAG);
dbgs() << "\n";
});

2
llvm/lib/Target/Hexagon/RDFLiveness.cpp
View File

@ -870,7 +870,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
}
if (Trace) {
dbgs() << "\n-- BB#" << B->getNumber() << ": " << LLVM_FUNCTION_NAME
dbgs() << "\n-- BB#" << B->getNumber() << ": " << __func__
<< " after recursion into: {";
for (auto I : *N)
dbgs() << ' ' << I->getBlock()->getNumber();