forked from OSchip/llvm-project
[X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROUNDPSY* and VROUNDPDY*. Fix itinerary mistake on all memory forms of VROUNDPD
This makes the Y position consistent with other instructions. This should have been NFC, but while refactoring the multiclass I noticed that VROUNDPD memory forms were using the register itinerary. llvm-svn: 328254
This commit is contained in:
Craig Topper
parent
b9d3d30e22
commit
40d3b32e12
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@ -793,8 +793,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
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{ X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
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{ X86::VPTESTYrr, X86::VPTESTYrm, 0 },
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{ X86::VRCPPSYr, X86::VRCPPSYm, 0 },
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{ X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
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{ X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
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{ X86::VROUNDPDYr, X86::VROUNDPDYm, 0 },
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{ X86::VROUNDPSYr, X86::VROUNDPSYm, 0 },
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{ X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
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{ X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
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{ X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
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@ -5863,49 +5863,35 @@ let Predicates = [UseAVX] in {
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// SSE4.1 - Round Instructions
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//===----------------------------------------------------------------------===//
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multiclass sse41_fp_unop_p<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
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def SSE_ROUNDPS : OpndItins<
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IIC_SSE_ROUNDPS_REG, IIC_SSE_ROUNDPS_MEM
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>;
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def SSE_ROUNDPD : OpndItins<
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IIC_SSE_ROUNDPD_REG, IIC_SSE_ROUNDPD_MEM
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>;
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multiclass sse41_fp_unop_p<bits<8> opc, string OpcodeStr,
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X86MemOperand x86memop, RegisterClass RC,
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ValueType VT32, ValueType VT64,
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PatFrag mem_frag32, PatFrag mem_frag64,
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SDNode OpNode> {
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let ExeDomain = SSEPackedSingle in {
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ValueType VT, PatFrag mem_frag, SDNode OpNode,
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OpndItins itins> {
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// Intrinsic operation, reg.
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// Vector intrinsic operation, reg
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def PSr : SS4AIi8<opcps, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
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!strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (VT32 (OpNode RC:$src1, imm:$src2)))],
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IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
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def r : SS4AIi8<opc, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (VT (OpNode RC:$src1, imm:$src2)))],
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itins.rr>, Sched<[WriteFAdd]>;
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// Vector intrinsic operation, mem
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def PSm : SS4AIi8<opcps, MRMSrcMem,
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(outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
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!strconcat(OpcodeStr,
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"ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst,
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(VT32 (OpNode (mem_frag32 addr:$src1),imm:$src2)))],
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IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
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} // ExeDomain = SSEPackedSingle
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let ExeDomain = SSEPackedDouble in {
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// Vector intrinsic operation, reg
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def PDr : SS4AIi8<opcpd, MRMSrcReg,
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(outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
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!strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst, (VT64 (OpNode RC:$src1, imm:$src2)))],
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IIC_SSE_ROUNDPD_REG>, Sched<[WriteFAdd]>;
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// Vector intrinsic operation, mem
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def PDm : SS4AIi8<opcpd, MRMSrcMem,
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(outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
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!strconcat(OpcodeStr,
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"pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst,
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(VT64 (OpNode (mem_frag64 addr:$src1),imm:$src2)))],
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IIC_SSE_ROUNDPD_REG>, Sched<[WriteFAddLd]>;
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} // ExeDomain = SSEPackedDouble
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def m : SS4AIi8<opc, MRMSrcMem,
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(outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set RC:$dst,
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(VT (OpNode (mem_frag addr:$src1),imm:$src2)))],
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itins.rm>, Sched<[WriteFAddLd]>;
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}
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multiclass avx_fp_unop_rm<bits<8> opcss, bits<8> opcsd,
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@ -6026,13 +6012,24 @@ let ExeDomain = SSEPackedDouble, isCodeGenOnly = 1 in {
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// FP round - roundss, roundps, roundsd, roundpd
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let Predicates = [HasAVX, NoVLX] in {
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// Intrinsic form
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defm VROUND : sse41_fp_unop_p<0x08, 0x09, "vround", f128mem, VR128, v4f32,
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v2f64, loadv4f32, loadv2f64, X86VRndScale>,
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VEX, VEX_WIG;
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defm VROUNDY : sse41_fp_unop_p<0x08, 0x09, "vround", f256mem, VR256, v8f32,
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v4f64, loadv8f32, loadv4f64, X86VRndScale>,
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VEX, VEX_L, VEX_WIG;
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let ExeDomain = SSEPackedSingle in {
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// Intrinsic form
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defm VROUNDPS : sse41_fp_unop_p<0x08, "vroundps", f128mem, VR128, v4f32,
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loadv4f32, X86VRndScale, SSE_ROUNDPS>,
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VEX, VEX_WIG;
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defm VROUNDPSY : sse41_fp_unop_p<0x08, "vroundps", f256mem, VR256, v8f32,
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loadv8f32, X86VRndScale, SSE_ROUNDPS>,
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VEX, VEX_L, VEX_WIG;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VROUNDPD : sse41_fp_unop_p<0x09, "vroundpd", f128mem, VR128, v2f64,
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loadv2f64, X86VRndScale, SSE_ROUNDPD>,
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VEX, VEX_WIG;
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defm VROUNDPDY : sse41_fp_unop_p<0x09, "vroundpd", f256mem, VR256, v4f64,
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loadv4f64, X86VRndScale, SSE_ROUNDPD>,
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VEX, VEX_L, VEX_WIG;
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}
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}
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let Predicates = [HasAVX, NoAVX512] in {
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defm VROUND : sse41_fp_binop_s<0x0A, 0x0B, "vround", v4f32, v2f64,
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@ -6087,30 +6084,34 @@ let Predicates = [HasAVX, NoVLX] in {
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(VROUNDPDr VR128:$src, (i32 0xB))>;
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def : Pat<(v8f32 (ffloor VR256:$src)),
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(VROUNDYPSr VR256:$src, (i32 0x9))>;
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(VROUNDPSYr VR256:$src, (i32 0x9))>;
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def : Pat<(v8f32 (fnearbyint VR256:$src)),
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(VROUNDYPSr VR256:$src, (i32 0xC))>;
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(VROUNDPSYr VR256:$src, (i32 0xC))>;
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def : Pat<(v8f32 (fceil VR256:$src)),
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(VROUNDYPSr VR256:$src, (i32 0xA))>;
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(VROUNDPSYr VR256:$src, (i32 0xA))>;
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def : Pat<(v8f32 (frint VR256:$src)),
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(VROUNDYPSr VR256:$src, (i32 0x4))>;
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(VROUNDPSYr VR256:$src, (i32 0x4))>;
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def : Pat<(v8f32 (ftrunc VR256:$src)),
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(VROUNDYPSr VR256:$src, (i32 0xB))>;
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(VROUNDPSYr VR256:$src, (i32 0xB))>;
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def : Pat<(v4f64 (ffloor VR256:$src)),
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(VROUNDYPDr VR256:$src, (i32 0x9))>;
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(VROUNDPDYr VR256:$src, (i32 0x9))>;
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def : Pat<(v4f64 (fnearbyint VR256:$src)),
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(VROUNDYPDr VR256:$src, (i32 0xC))>;
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(VROUNDPDYr VR256:$src, (i32 0xC))>;
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def : Pat<(v4f64 (fceil VR256:$src)),
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(VROUNDYPDr VR256:$src, (i32 0xA))>;
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(VROUNDPDYr VR256:$src, (i32 0xA))>;
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def : Pat<(v4f64 (frint VR256:$src)),
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(VROUNDYPDr VR256:$src, (i32 0x4))>;
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(VROUNDPDYr VR256:$src, (i32 0x4))>;
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def : Pat<(v4f64 (ftrunc VR256:$src)),
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(VROUNDYPDr VR256:$src, (i32 0xB))>;
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(VROUNDPDYr VR256:$src, (i32 0xB))>;
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}
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defm ROUND : sse41_fp_unop_p<0x08, 0x09, "round", f128mem, VR128, v4f32, v2f64,
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memopv4f32, memopv2f64, X86VRndScale>;
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let ExeDomain = SSEPackedSingle in
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defm ROUNDPS : sse41_fp_unop_p<0x08, "roundps", f128mem, VR128, v4f32,
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memopv4f32, X86VRndScale, SSE_ROUNDPS>;
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let ExeDomain = SSEPackedDouble in
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defm ROUNDPD : sse41_fp_unop_p<0x09, "roundpd", f128mem, VR128, v2f64,
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memopv2f64, X86VRndScale, SSE_ROUNDPD>;
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defm ROUND : sse41_fp_unop_s<0x0A, 0x0B, "round">;
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@ -1742,8 +1742,8 @@ def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
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"VROUNDPSr",
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"VROUNDSDr",
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"VROUNDSSr",
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"VROUNDYPDr",
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"VROUNDYPSr")>;
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"VROUNDPDYr",
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"VROUNDPSYr")>;
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def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
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let Latency = 6;
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@ -3014,8 +3014,8 @@ def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
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"SUBR_FI32m",
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"SUB_FI16m",
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"SUB_FI32m",
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"VROUNDYPDm",
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"VROUNDYPSm")>;
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"VROUNDPDYm",
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"VROUNDPSYm")>;
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def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
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let Latency = 12;
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@ -555,8 +555,8 @@ def: InstRW<[HWWriteResGroup0], (instregex "VBROADCASTSSrm",
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"(V?)MOVUPSrm",
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"VPBROADCASTDrm",
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"VPBROADCASTQrm",
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"(V?)ROUND(Y?)PDr",
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"(V?)ROUND(Y?)PSr",
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"(V?)ROUNDPD(Y?)r",
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"(V?)ROUNDPS(Y?)r",
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"(V?)ROUNDSDr",
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"(V?)ROUNDSSr")>;
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@ -2787,8 +2787,8 @@ def: InstRW<[HWWriteResGroup103], (instregex "ADD_FI16m",
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"SUBR_FI32m",
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"SUB_FI16m",
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"SUB_FI32m",
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"VROUNDYPDm",
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"VROUNDYPSm")>;
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"VROUNDPDYm",
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"VROUNDPSYm")>;
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def HWWriteResGroup103_1 : SchedWriteRes<[HWPort1,HWPort23]> {
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let Latency = 12;
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@ -757,8 +757,8 @@ def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0",
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"(V?)ROUNDPSr",
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"(V?)ROUNDSDr",
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"(V?)ROUNDSSr",
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"VROUNDYPDr",
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"VROUNDYPSr",
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"VROUNDPDYr",
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"VROUNDPSYr",
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"VSUBPDYrr",
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"(V?)SUBPDrr",
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"VSUBPSYrr",
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@ -1853,8 +1853,8 @@ def: InstRW<[SBWriteResGroup101], (instregex "ADD_F32m",
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"VMAX(C?)PSYrm",
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"VMIN(C?)PDYrm",
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"VMIN(C?)PSYrm",
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"VROUNDYPDm",
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"VROUNDYPSm",
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"VROUNDPDYm",
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"VROUNDPSYm",
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"VSUBPDYrm",
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"VSUBPSYrm")>;
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@ -2406,8 +2406,8 @@ def: InstRW<[SKLWriteResGroup105], (instregex "ROUNDPDr",
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"VROUNDPSr",
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"VROUNDSDr",
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"VROUNDSSr",
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"VROUNDYPDr",
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"VROUNDYPSr")>;
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"VROUNDPDYr",
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"VROUNDPSYr")>;
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def SKLWriteResGroup105_2 : SchedWriteRes<[SKLPort01]> {
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let Latency = 10;
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@ -3231,8 +3231,8 @@ def SKLWriteResGroup172 : SchedWriteRes<[SKLPort23,SKLPort01]> {
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let NumMicroOps = 3;
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let ResourceCycles = [1,2];
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}
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def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDYPDm",
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"VROUNDYPSm")>;
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def: InstRW<[SKLWriteResGroup172], (instregex "VROUNDPDYm",
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"VROUNDPSYm")>;
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def SKLWriteResGroup172_2 : SchedWriteRes<[SKLPort23,SKLPort01]> {
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let Latency = 17;
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@ -3876,8 +3876,8 @@ def: InstRW<[SKXWriteResGroup116], (instregex "ROUNDPDr",
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"VROUNDPSr",
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"VROUNDSDr",
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"VROUNDSSr",
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"VROUNDYPDr",
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"VROUNDYPSr")>;
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"VROUNDPDYr",
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"VROUNDPSYr")>;
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def SKXWriteResGroup116_2 : SchedWriteRes<[SKXPort015]> {
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let Latency = 10;
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@ -5555,8 +5555,8 @@ def: InstRW<[SKXWriteResGroup192], (instregex "VRNDSCALEPDZ256rm(b?)i(k?)(z?)",
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"VRNDSCALEPDZrm(b?)i(k?)(z?)",
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"VRNDSCALEPSZ256rm(b?)i(k?)(z?)",
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"VRNDSCALEPSZrm(b?)i(k?)(z?)",
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"VROUNDYPDm",
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"VROUNDYPSm")>;
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"VROUNDPDYm",
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"VROUNDPSYm")>;
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def SKXWriteResGroup192_2 : SchedWriteRes<[SKXPort23,SKXPort015]> {
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let Latency = 17;
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@ -599,7 +599,7 @@ def JWriteVCVTY: SchedWriteRes<[JFPU1, JSTC]> {
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}
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def : InstRW<[JWriteVCVTY], (instrs VCVTDQ2PDYrr, VCVTDQ2PSYrr,
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VCVTPS2DQYrr, VCVTTPS2DQYrr,
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VROUNDYPDr, VROUNDYPSr)>;
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VROUNDPDYr, VROUNDPSYr)>;
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def JWriteVCVTYLd: SchedWriteRes<[JLAGU, JFPU1, JSTC]> {
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let Latency = 8;
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@ -607,7 +607,7 @@ def JWriteVCVTYLd: SchedWriteRes<[JLAGU, JFPU1, JSTC]> {
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}
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def : InstRW<[JWriteVCVTYLd, ReadAfterLd], (instrs VCVTDQ2PDYrm, VCVTDQ2PSYrm,
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VCVTPS2DQYrm, VCVTTPS2DQYrm,
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VROUNDYPDm, VROUNDYPSm)>;
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VROUNDPDYm, VROUNDPSYm)>;
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def JWriteVMOVNTDQSt: SchedWriteRes<[JFPU1, JSTC, JSAGU]> {
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let Latency = 2;
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@ -4132,8 +4132,8 @@ define <4 x double> @test_roundpd(<4 x double> %a0, <4 x double> *%a1) {
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;
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; ZNVER1-LABEL: test_roundpd:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [11:1.00]
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; ZNVER1-NEXT: vroundpd $7, %ymm0, %ymm0 # sched: [4:1.00]
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; ZNVER1-NEXT: vroundpd $7, (%rdi), %ymm1 # sched: [10:1.00]
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; ZNVER1-NEXT: vroundpd $7, %ymm0, %ymm0 # sched: [3:1.00]
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; ZNVER1-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> %a0, i32 7)
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@ -4196,8 +4196,8 @@ define <8 x float> @test_roundps(<8 x float> %a0, <8 x float> *%a1) {
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;
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; ZNVER1-LABEL: test_roundps:
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; ZNVER1: # %bb.0:
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; ZNVER1-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [11:1.00]
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; ZNVER1-NEXT: vroundps $7, %ymm0, %ymm0 # sched: [4:1.00]
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; ZNVER1-NEXT: vroundps $7, (%rdi), %ymm1 # sched: [10:1.00]
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; ZNVER1-NEXT: vroundps $7, %ymm0, %ymm0 # sched: [3:1.00]
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; ZNVER1-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:1.00]
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; ZNVER1-NEXT: retq # sched: [1:0.50]
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%1 = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7)
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@ -169,10 +169,10 @@ void X86EVEX2VEXTablesEmitter::printTable(const std::vector<Entry> &Table,
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{"VRNDSCALEPDZ128rmi", "VROUNDPDm", true},
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{"VRNDSCALEPSZ128rri", "VROUNDPSr", true},
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{"VRNDSCALEPSZ128rmi", "VROUNDPSm", true},
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{"VRNDSCALEPDZ256rri", "VROUNDYPDr", false},
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{"VRNDSCALEPDZ256rmi", "VROUNDYPDm", false},
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{"VRNDSCALEPSZ256rri", "VROUNDYPSr", false},
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{"VRNDSCALEPSZ256rmi", "VROUNDYPSm", false},
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||||
{"VRNDSCALEPDZ256rri", "VROUNDPDYr", false},
|
||||
{"VRNDSCALEPDZ256rmi", "VROUNDPDYm", false},
|
||||
{"VRNDSCALEPSZ256rri", "VROUNDPSYr", false},
|
||||
{"VRNDSCALEPSZ256rmi", "VROUNDPSYm", false},
|
||||
{"VRNDSCALESDr", "VROUNDSDr", true},
|
||||
{"VRNDSCALESDm", "VROUNDSDm", true},
|
||||
{"VRNDSCALESSr", "VROUNDSSr", true},
|
||||
|
|
|
|||
Loading…
Reference in New Issue