forked from OSchip/llvm-project
[Hexagon] Distribute disjoint intervals at the end of expand-condsets
This fixes https://github.com/llvm/llvm-project/issues/56050.
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@ -210,6 +210,7 @@ namespace {
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void removeInstr(MachineInstr &MI);
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void updateLiveness(const std::set<Register> &RegSet, bool Recalc,
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bool UpdateKills, bool UpdateDeads);
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void distributeLiveIntervals(const std::set<Register> &Regs);
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unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
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MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
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@ -574,6 +575,27 @@ void HexagonExpandCondsets::updateLiveness(const std::set<Register> &RegSet,
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}
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}
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void HexagonExpandCondsets::distributeLiveIntervals(
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const std::set<Register> &Regs) {
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ConnectedVNInfoEqClasses EQC(*LIS);
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for (Register R : Regs) {
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if (!R.isVirtual())
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continue;
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LiveInterval &LI = LIS->getInterval(R);
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unsigned NumComp = EQC.Classify(LI);
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if (NumComp == 1)
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continue;
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SmallVector<LiveInterval*> NewLIs;
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const TargetRegisterClass *RC = MRI->getRegClass(LI.reg());
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for (unsigned I = 1; I < NumComp; ++I) {
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Register NewR = MRI->createVirtualRegister(RC);
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NewLIs.push_back(&LIS->createEmptyInterval(NewR));
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}
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EQC.Distribute(LI, NewLIs.begin(), *MRI);
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}
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}
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/// Get the opcode for a conditional transfer of the value in SO (source
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/// operand). The condition (true/false) is given in Cond.
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unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
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@ -1320,6 +1342,9 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
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PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
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updateLiveness(PredUpd, true, true, true);
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if (Changed)
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distributeLiveIntervals(PredUpd);
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LLVM_DEBUG({
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if (Changed)
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LIS->print(dbgs() << "After expand-condsets\n",
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@ -31,8 +31,11 @@ body: |
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%0 = COPY $p0
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%1 = COPY $r0
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%2 = COPY $d0
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; This copy is added by distributing disjoint live interval. Check
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; for it to make sure %4 is the right thing.
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; CHECK: %4:doubleregs = COPY $d0
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; Check that this instruction is unchanged (remains unpredicated)
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; CHECK: %3:intregs = A2_addi %2.isub_hi, 1
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; CHECK: %3:intregs = A2_addi %4.isub_hi, 1
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%3 = A2_addi %2.isub_hi, 1
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undef %2.isub_lo = C2_mux %0, %2.isub_lo, %1
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%2.isub_hi = C2_muxir %0, %3, 0
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