[Hexagon] Distribute disjoint intervals at the end of expand-condsets

This fixes https://github.com/llvm/llvm-project/issues/56050.
This commit is contained in:
Krzysztof Parzyszek 2022-08-14 15:57:44 -05:00
parent 98bd252432
commit 40ba78679d
2 changed files with 29 additions and 1 deletions

View File

@ -210,6 +210,7 @@ namespace {
void removeInstr(MachineInstr &MI);
void updateLiveness(const std::set<Register> &RegSet, bool Recalc,
bool UpdateKills, bool UpdateDeads);
void distributeLiveIntervals(const std::set<Register> &Regs);
unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
@ -574,6 +575,27 @@ void HexagonExpandCondsets::updateLiveness(const std::set<Register> &RegSet,
}
}
void HexagonExpandCondsets::distributeLiveIntervals(
const std::set<Register> &Regs) {
ConnectedVNInfoEqClasses EQC(*LIS);
for (Register R : Regs) {
if (!R.isVirtual())
continue;
LiveInterval &LI = LIS->getInterval(R);
unsigned NumComp = EQC.Classify(LI);
if (NumComp == 1)
continue;
SmallVector<LiveInterval*> NewLIs;
const TargetRegisterClass *RC = MRI->getRegClass(LI.reg());
for (unsigned I = 1; I < NumComp; ++I) {
Register NewR = MRI->createVirtualRegister(RC);
NewLIs.push_back(&LIS->createEmptyInterval(NewR));
}
EQC.Distribute(LI, NewLIs.begin(), *MRI);
}
}
/// Get the opcode for a conditional transfer of the value in SO (source
/// operand). The condition (true/false) is given in Cond.
unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
@ -1320,6 +1342,9 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
updateLiveness(PredUpd, true, true, true);
if (Changed)
distributeLiveIntervals(PredUpd);
LLVM_DEBUG({
if (Changed)
LIS->print(dbgs() << "After expand-condsets\n",

View File

@ -31,8 +31,11 @@ body: |
%0 = COPY $p0
%1 = COPY $r0
%2 = COPY $d0
; This copy is added by distributing disjoint live interval. Check
; for it to make sure %4 is the right thing.
; CHECK: %4:doubleregs = COPY $d0
; Check that this instruction is unchanged (remains unpredicated)
; CHECK: %3:intregs = A2_addi %2.isub_hi, 1
; CHECK: %3:intregs = A2_addi %4.isub_hi, 1
%3 = A2_addi %2.isub_hi, 1
undef %2.isub_lo = C2_mux %0, %2.isub_lo, %1
%2.isub_hi = C2_muxir %0, %3, 0