forked from OSchip/llvm-project
[AMDGPU][MC] Fix for Bugs 28200, 28202 + LIT tests
Fixed several related issues with VOP3 fp modifiers. Reviewers: artem.tamazov Differential Revision: https://reviews.llvm.org/D30821 llvm-svn: 298255
This commit is contained in:
Dmitry Preobrazhensky
parent
d79253a9f7
commit
40af9c35d3
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@ -542,9 +542,11 @@ public:
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return getModifiers().hasIntModifiers();
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}
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uint64_t applyInputFPModifiers(uint64_t Val, unsigned Size) const;
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void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const;
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void addLiteralImmOperand(MCInst &Inst, int64_t Val) const;
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void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const;
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template <unsigned Bitwidth>
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void addKImmFPOperands(MCInst &Inst, unsigned N) const;
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@ -1173,6 +1175,13 @@ bool AMDGPUOperand::isLiteralImm(MVT type) const {
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if (!Imm.IsFPImm) {
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// We got int literal token.
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if (type == MVT::f64 && hasFPModifiers()) {
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// Cannot apply fp modifiers to int literals preserving the same semantics
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// for VOP1/2/C and VOP3 because of integer truncation. To avoid ambiguity,
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// disable these cases.
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return false;
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}
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unsigned Size = type.getSizeInBits();
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if (Size == 64)
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Size = 32;
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@ -1202,33 +1211,48 @@ bool AMDGPUOperand::isRegClass(unsigned RCID) const {
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return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());
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}
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void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {
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int64_t Val = Imm.Val;
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if (isImmTy(ImmTyNone) && ApplyModifiers && Imm.Mods.hasFPModifiers() && Imm.Mods.Neg) {
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// Apply modifiers to immediate value. Only negate can get here
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if (Imm.IsFPImm) {
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APFloat F(BitsToDouble(Val));
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F.changeSign();
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Val = F.bitcastToAPInt().getZExtValue();
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} else {
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Val = -Val;
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}
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uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const
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{
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assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());
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assert(Size == 2 || Size == 4 || Size == 8);
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const uint64_t FpSignMask = (1ULL << (Size * 8 - 1));
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if (Imm.Mods.Abs) {
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Val &= ~FpSignMask;
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}
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if (Imm.Mods.Neg) {
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Val ^= FpSignMask;
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}
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return Val;
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}
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void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {
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if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),
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Inst.getNumOperands())) {
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addLiteralImmOperand(Inst, Val);
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addLiteralImmOperand(Inst, Imm.Val,
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ApplyModifiers &
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isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());
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} else {
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Inst.addOperand(MCOperand::createImm(Val));
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assert(!isImmTy(ImmTyNone) || !hasModifiers());
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Inst.addOperand(MCOperand::createImm(Imm.Val));
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}
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}
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void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val) const {
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void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const {
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const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
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auto OpNum = Inst.getNumOperands();
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// Check that this operand accepts literals
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assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));
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if (ApplyModifiers) {
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assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));
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const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);
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Val = applyInputFPModifiers(Val, Size);
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}
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APInt Literal(64, Val);
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uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType;
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@ -1694,14 +1718,44 @@ AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands) {
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OperandMatchResultTy
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AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
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bool AllowImm) {
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// XXX: During parsing we can't determine if minus sign means
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// negate-modifier or negative immediate value.
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// By default we suppose it is modifier.
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bool Negate = false, Abs = false, Abs2 = false;
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bool Negate = false, Negate2 = false, Abs = false, Abs2 = false;
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if (getLexer().getKind()== AsmToken::Minus) {
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const AsmToken NextToken = getLexer().peekTok();
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// Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead.
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if (NextToken.is(AsmToken::Minus)) {
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Error(Parser.getTok().getLoc(), "invalid syntax, expected 'neg' modifier");
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return MatchOperand_ParseFail;
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}
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// '-' followed by an integer literal N should be interpreted as integer
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// negation rather than a floating-point NEG modifier applied to N.
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// Beside being contr-intuitive, such use of floating-point NEG modifier
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// results in different meaning of integer literals used with VOP1/2/C
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// and VOP3, for example:
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// v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF
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// v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001
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// Negative fp literals should be handled likewise for unifomtity
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if (!NextToken.is(AsmToken::Integer) && !NextToken.is(AsmToken::Real)) {
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Parser.Lex();
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Negate = true;
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}
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}
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if (getLexer().getKind() == AsmToken::Identifier &&
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Parser.getTok().getString() == "neg") {
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if (Negate) {
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Error(Parser.getTok().getLoc(), "expected register or immediate");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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Negate2 = true;
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if (getLexer().isNot(AsmToken::LParen)) {
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Error(Parser.getTok().getLoc(), "expected left paren after neg");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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Negate = true;
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}
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if (getLexer().getKind() == AsmToken::Identifier &&
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@ -1735,9 +1789,6 @@ AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
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}
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AMDGPUOperand::Modifiers Mods;
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if (Negate) {
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Mods.Neg = true;
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}
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if (Abs) {
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if (getLexer().getKind() != AsmToken::Pipe) {
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Error(Parser.getTok().getLoc(), "expected vertical bar");
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@ -1755,6 +1806,17 @@ AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
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Mods.Abs = true;
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}
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if (Negate) {
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Mods.Neg = true;
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} else if (Negate2) {
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if (getLexer().isNot(AsmToken::RParen)) {
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Error(Parser.getTok().getLoc(), "expected closing parentheses");
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return MatchOperand_ParseFail;
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}
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Parser.Lex();
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Mods.Neg = true;
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}
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if (Mods.hasFPModifiers()) {
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AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
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Op.setModifiers(Mods);
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@ -543,13 +543,34 @@ void AMDGPUInstPrinter::printOperandAndFPInputMods(const MCInst *MI,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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unsigned InputModifiers = MI->getOperand(OpNo).getImm();
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if (InputModifiers & SISrcMods::NEG)
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O << '-';
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// Use 'neg(...)' instead of '-' to avoid ambiguity.
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// This is important for integer literals because
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// -1 is not the same value as neg(1).
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bool NegMnemo = false;
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if (InputModifiers & SISrcMods::NEG) {
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if (OpNo + 1 < MI->getNumOperands() &&
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(InputModifiers & SISrcMods::ABS) == 0) {
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const MCOperand &Op = MI->getOperand(OpNo + 1);
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NegMnemo = Op.isImm() || Op.isFPImm();
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}
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if (NegMnemo) {
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O << "neg(";
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} else {
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O << '-';
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}
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}
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if (InputModifiers & SISrcMods::ABS)
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O << '|';
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printOperand(MI, OpNo + 1, STI, O);
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if (InputModifiers & SISrcMods::ABS)
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O << '|';
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if (NegMnemo) {
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O << ')';
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}
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}
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void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
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@ -248,12 +248,12 @@ v_trunc_f32_e32 v0, -13
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// VI: v_fract_f64_e32 v[0:1], -13 ; encoding: [0xcd,0x64,0x00,0x7e]
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v_fract_f64_e32 v[0:1], -13
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// SICI: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0x42,0xd3,0x8d,0x00,0x00,0x20]
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// VI: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0x5c,0xd1,0x8d,0x00,0x00,0x20]
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// SICI: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0x42,0xd3,0xcd,0x00,0x00,0x00]
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// VI: v_trunc_f32_e64 v0, -13 ; encoding: [0x00,0x00,0x5c,0xd1,0xcd,0x00,0x00,0x00]
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v_trunc_f32_e64 v0, -13
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// SICI: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0x7c,0xd3,0x8d,0x00,0x00,0x20]
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// VI: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0x72,0xd1,0x8d,0x00,0x00,0x20]
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// SICI: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0x7c,0xd3,0xcd,0x00,0x00,0x00]
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// VI: v_fract_f64_e64 v[0:1], -13 ; encoding: [0x00,0x00,0x72,0xd1,0xcd,0x00,0x00,0x00]
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v_fract_f64_e64 v[0:1], -13
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// SICI: v_trunc_f32_e32 v0, 35 ; encoding: [0xa3,0x42,0x00,0x7e]
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@ -0,0 +1,15 @@
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// RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck %s
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//---------------------------------------------------------------------------//
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// VOP3 Modifiers
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//---------------------------------------------------------------------------//
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// 'neg(1)' cannot be encoded as 32-bit literal while preserving e64 semantics
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v_ceil_f64_e32 v[0:1], neg(1)
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// CHECK: error: invalid operand for instruction
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v_ceil_f32 v0, --1
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// CHECK: error: invalid syntax, expected 'neg' modifier
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v_ceil_f16 v0, abs(neg(1))
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// CHECK: error: not a valid operand
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@ -0,0 +1,258 @@
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// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s
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//---------------------------------------------------------------------------//
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// VOP1/VOP3 F16
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//---------------------------------------------------------------------------//
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v_ceil_f16 v0, -1
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// CHECK: [0xc1,0x8a,0x00,0x7e]
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v_ceil_f16 v0, -2
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// CHECK: [0xc2,0x8a,0x00,0x7e]
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v_ceil_f16 v0, -16
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// CHECK: [0xd0,0x8a,0x00,0x7e]
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v_ceil_f16 v0, -0.5
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// CHECK: [0xf1,0x8a,0x00,0x7e]
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v_ceil_f16 v0, -1.0
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// CHECK: [0xf3,0x8a,0x00,0x7e]
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v_ceil_f16 v0, -2.0
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// CHECK: [0xf5,0x8a,0x00,0x7e]
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v_ceil_f16 v0, -4.0
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// CHECK: [0xf7,0x8a,0x00,0x7e]
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// Arbitrary f16 literal in hex
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v_ceil_f16 v0, 0xabcd
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// CHECK: [0xff,0x8a,0x00,0x7e,0xcd,0xab,0x00,0x00]
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// '-' is a part of hex literal (not a 'neg' modifier)
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v_ceil_f16 v0, -0x5433
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// CHECK: [0xff,0x8a,0x00,0x7e,0xcd,0xab,0x00,0x00]
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v_ceil_f16 v0, abs(0xabcd)
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// CHECK: [0xff,0x8a,0x00,0x7e,0xcd,0x2b,0x00,0x00]
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v_ceil_f16 v0, neg(0xabcd)
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// CHECK: [0xff,0x8a,0x00,0x7e,0xcd,0x2b,0x00,0x00]
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v_ceil_f16 v0, neg(abs(0xabcd))
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// CHECK: [0xff,0x8a,0x00,0x7e,0xcd,0xab,0x00,0x00]
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v_ceil_f16 v0, -abs(0xabcd)
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// CHECK: [0xff,0x8a,0x00,0x7e,0xcd,0xab,0x00,0x00]
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// 1/(2*pi) encoded as inline constant in VOP1
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v_ceil_f16 v0, 0x3118
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// CHECK: [0xf8,0x8a,0x00,0x7e]
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// 1/(2*pi) encoded as inline constant in VOP3
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v_ceil_f16_e64 v0, 0x3118
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// CHECK: [0x00,0x00,0x85,0xd1,0xf8,0x00,0x00,0x00]
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// neg(-1/(2*pi)) = 1/(2*pi)
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v_ceil_f16 v0, neg(0xb118)
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// CHECK: [0xf8,0x8a,0x00,0x7e]
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// -1/(2*pi) cannot be encoded as inline constant in VOP1
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v_ceil_f16 v0, 0xb118
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// CHECK: [0xff,0x8a,0x00,0x7e,0x18,0xb1,0x00,0x00]
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// -1/(2*pi) cannot be encoded as inline constant in VOP1
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v_ceil_f16 v0, neg(0x3118)
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// CHECK: [0xff,0x8a,0x00,0x7e,0x18,0xb1,0x00,0x00]
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// -1/(2*pi) can be encoded as inline constant w/ modifiers in VOP3
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v_ceil_f16_e64 v0, neg(0x3118)
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// CHECK: [0x00,0x00,0x85,0xd1,0xf8,0x00,0x00,0x20]
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v_ceil_f16_e64 v0, abs(0x3118)
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// CHECK: 0x00,0x01,0x85,0xd1,0xf8,0x00,0x00,0x00]
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v_ceil_f16_e64 v0, neg(abs(0x3118))
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// CHECK: [0x00,0x01,0x85,0xd1,0xf8,0x00,0x00,0x20]
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v_ceil_f16_e64 v0, neg(|v1|)
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// CHECK: [0x00,0x01,0x85,0xd1,0x01,0x01,0x00,0x20]
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v_ceil_f16_e64 v0, -|v1|
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// CHECK: [0x00,0x01,0x85,0xd1,0x01,0x01,0x00,0x20]
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//---------------------------------------------------------------------------//
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// VOP1/VOP3 F64
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//---------------------------------------------------------------------------//
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// Encoded as inline constant 1 with 'neg' modifier
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v_ceil_f64 v[0:1], neg(1)
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// CHECK: [0x00,0x00,0x58,0xd1,0x81,0x00,0x00,0x20]
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// Encoded as inline constant -1 with 'neg' modifier
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v_ceil_f64 v[0:1], neg(-1)
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// CHECK: [0x00,0x00,0x58,0xd1,0xc1,0x00,0x00,0x20]
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v_ceil_f64_e32 v[0:1], 1.0
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// CHECK: [0xf2,0x30,0x00,0x7e]
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// abs(1.0) = 1.0
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v_ceil_f64_e32 v[0:1], abs(1.0)
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// CHECK: [0xf2,0x30,0x00,0x7e]
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// neg(1.0) = -1.0
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v_ceil_f64_e32 v[0:1], neg(1.0)
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// CHECK: [0xf3,0x30,0x00,0x7e]
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// 1/(2*pi) encoded as inline constant in VOP1
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v_ceil_f64 v[0:1], 0x3fc45f306dc9c882
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// CHECK: [0xf8,0x30,0x00,0x7e]
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// 1/(2*pi) encoded as inline constant in VOP3
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v_ceil_f64_e64 v[0:1], 0x3fc45f306dc9c882
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// CHECK: [0x00,0x00,0x58,0xd1,0xf8,0x00,0x00,0x00]
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// -1/(2*pi) cannot be encoded as inline constant in VOP1.
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// It cannot be encoded as literal either due to int literal rules.
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// So it is encoded as VOP3
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v_ceil_f64 v[0:1], abs(0x3fc45f306dc9c882)
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// CHECK: [0x00,0x01,0x58,0xd1,0xf8,0x00,0x00,0x00]
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v_ceil_f64 v[0:1], neg(abs(0x3fc45f306dc9c882))
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// CHECK: [0x00,0x01,0x58,0xd1,0xf8,0x00,0x00,0x20]
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//---------------------------------------------------------------------------//
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// VOP2/VOP3 F32
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//---------------------------------------------------------------------------//
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v_add_f32 v5, -1, v2
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// CHECK: [0xc1,0x04,0x0a,0x02]
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v_add_f32 v5, -16, v2
|
||||
// CHECK: [0xd0,0x04,0x0a,0x02]
|
||||
|
||||
v_add_f32 v5, 0x3e22f983, v2
|
||||
// CHECK: [0xf8,0x04,0x0a,0x02]
|
||||
|
||||
// abs(1/(2*pi)) = 1/(2*pi)
|
||||
v_add_f32 v5, abs(0x3e22f983), v2
|
||||
// CHECK: [0xf8,0x04,0x0a,0x02]
|
||||
|
||||
// neg(-1/(2*pi)) = 1/(2*pi)
|
||||
v_add_f32 v5, neg(0xbe22f983), v2
|
||||
// CHECK: [0xf8,0x04,0x0a,0x02]
|
||||
|
||||
// -1/(2*pi) cannot be encoded as inline constant in VOP1
|
||||
v_add_f32 v5, neg(0x3e22f983), v2
|
||||
// CHECK: [0xff,0x04,0x0a,0x02,0x83,0xf9,0x22,0xbe]
|
||||
|
||||
|
||||
v_add_f32_e64 v0, -2, s0
|
||||
// CHECK: [0x00,0x00,0x01,0xd1,0xc2,0x00,0x00,0x00]
|
||||
|
||||
v_add_f32_e64 v0, -16, s0
|
||||
// CHECK: [0x00,0x00,0x01,0xd1,0xd0,0x00,0x00,0x00]
|
||||
|
||||
v_add_f32_e64 v0, -0.5, s0
|
||||
// CHECK: [0x00,0x00,0x01,0xd1,0xf1,0x00,0x00,0x00]
|
||||
|
||||
v_add_f32_e64 v0, -1.0, s0
|
||||
// CHECK: [0x00,0x00,0x01,0xd1,0xf3,0x00,0x00,0x00]
|
||||
|
||||
v_add_f32_e64 v0, -2.0, s0
|
||||
// CHECK: [0x00,0x00,0x01,0xd1,0xf5,0x00,0x00,0x00]
|
||||
|
||||
v_add_f32_e64 v0, -4.0, s0
|
||||
// CHECK: [0x00,0x00,0x01,0xd1,0xf7,0x00,0x00,0x00]
|
||||
|
||||
v_add_f32_e64 v0, 0x3e22f983, s0
|
||||
// CHECK: [0x00,0x00,0x01,0xd1,0xf8,0x00,0x00,0x00]
|
||||
|
||||
v_add_f32_e64 v0, neg(0x3e22f983), s0
|
||||
// CHECK: [0x00,0x00,0x01,0xd1,0xf8,0x00,0x00,0x20]
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// VOPC/VOP3
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
v_cmp_eq_f16 vcc, -1, v0
|
||||
// CHECK: [0xc1,0x00,0x44,0x7c]
|
||||
|
||||
v_cmp_eq_f16_e64 s[0:1], s0, -1
|
||||
// CHECK: [0x00,0x00,0x22,0xd0,0x00,0x82,0x01,0x00]
|
||||
|
||||
v_cmp_eq_f16_e64 s[0:1], s0, 0x3118
|
||||
// CHECK: [0x00,0x00,0x22,0xd0,0x00,0xf0,0x01,0x00]
|
||||
|
||||
v_cmp_eq_f16_e64 s[0:1], s0, neg(0x3118)
|
||||
// CHECK: [0x00,0x00,0x22,0xd0,0x00,0xf0,0x01,0x40]
|
||||
|
||||
v_cmp_eq_f32 vcc, -4.0, v0
|
||||
// CHECK: [0xf7,0x00,0x84,0x7c]
|
||||
|
||||
// 1/(2*pi) can be encoded as inline constant
|
||||
v_cmp_eq_f32 vcc, 0x3e22f983, v0
|
||||
// CHECK: [0xf8,0x00,0x84,0x7c]
|
||||
|
||||
// -1/(2*pi) cannot be encoded as inline constant in VOPC
|
||||
v_cmp_eq_f32 vcc, neg(0x3e22f983), v0
|
||||
// CHECK: [0xff,0x00,0x84,0x7c,0x83,0xf9,0x22,0xbe]
|
||||
|
||||
// abs(1/(2*pi)) = 1/(2*pi)
|
||||
v_cmp_eq_f32 vcc, abs(0x3e22f983), v0
|
||||
// CHECK: [0xf8,0x00,0x84,0x7c]
|
||||
|
||||
// -1/(2*pi) can be encoded as inline constant w/ modifiers in VOP3
|
||||
v_cmp_eq_f32_e64 vcc, neg(0x3e22f983), v0
|
||||
// CHECK: [0x6a,0x00,0x42,0xd0,0xf8,0x00,0x02,0x20]
|
||||
|
||||
v_cmp_eq_f32_e64 vcc, v0, abs(0x3e22f983)
|
||||
// CHECK: [0x6a,0x02,0x42,0xd0,0x00,0xf1,0x01,0x00]
|
||||
|
||||
v_cmp_eq_f32_e64 vcc, v0, -abs(0x3e22f983)
|
||||
// CHECK: [0x6a,0x02,0x42,0xd0,0x00,0xf1,0x01,0x40]
|
||||
|
||||
//---------------------------------------------------------------------------//
|
||||
// VOP3
|
||||
//---------------------------------------------------------------------------//
|
||||
|
||||
v_add_f64 v[0:1], s[0:1], -1
|
||||
// CHECK: [0x00,0x00,0x80,0xd2,0x00,0x82,0x01,0x00]
|
||||
|
||||
v_add_f64 v[0:1], s[0:1], -16
|
||||
// CHECK: [0x00,0x00,0x80,0xd2,0x00,0xa0,0x01,0x00]
|
||||
|
||||
v_add_f64 v[0:1], s[0:1], -0.5
|
||||
// CHECK: [0x00,0x00,0x80,0xd2,0x00,0xe2,0x01,0x00]
|
||||
|
||||
v_add_f64 v[0:1], s[0:1], -1.0
|
||||
// CHECK: [0x00,0x00,0x80,0xd2,0x00,0xe6,0x01,0x00]
|
||||
|
||||
v_add_f64 v[0:1], s[0:1], -2.0
|
||||
// CHECK: [0x00,0x00,0x80,0xd2,0x00,0xea,0x01,0x00]
|
||||
|
||||
v_add_f64 v[0:1], s[0:1], -4.0
|
||||
// CHECK: [0x00,0x00,0x80,0xd2,0x00,0xee,0x01,0x00]
|
||||
|
||||
v_add_f64 v[4:5], s[0:1], 0x3fc45f306dc9c882
|
||||
// CHECK: [0x04,0x00,0x80,0xd2,0x00,0xf0,0x01,0x00]
|
||||
|
||||
v_add_f64 v[4:5], s[0:1], neg(0x3fc45f306dc9c882)
|
||||
// CHECK: [0x04,0x00,0x80,0xd2,0x00,0xf0,0x01,0x40]
|
||||
|
||||
|
||||
v_cubeid_f32 v0, s0, s0, -1
|
||||
// CHECK: [0x00,0x00,0xc4,0xd1,0x00,0x00,0x04,0x03]
|
||||
|
||||
v_cubeid_f32 v0, s0, s0, -4.0
|
||||
// CHECK: [0x00,0x00,0xc4,0xd1,0x00,0x00,0xdc,0x03]
|
||||
|
||||
v_cubeid_f32 v0, s0, s0, 0x3e22f983
|
||||
// CHECK: [0x00,0x00,0xc4,0xd1,0x00,0x00,0xe0,0x03]
|
||||
|
||||
v_cubeid_f32 v0, s0, s0, neg(0x3e22f983)
|
||||
// CHECK: [0x00,0x00,0xc4,0xd1,0x00,0x00,0xe0,0x83]
|
||||
|
||||
v_cubeid_f32 v0, s0, s0, abs(0x3e22f983)
|
||||
// CHECK: [0x00,0x04,0xc4,0xd1,0x00,0x00,0xe0,0x03]
|
||||
|
|
@ -265,11 +265,11 @@ v_mac_f16_e64 v0, 0.5, flat_scratch_lo
|
|||
|
||||
v_mac_f16_e64 v0, -4.0, flat_scratch_lo
|
||||
// NOSICI: error:
|
||||
// VI: v_mac_f16_e64 v0, -4.0, flat_scratch_lo ; encoding: [0x00,0x00,0x23,0xd1,0xf6,0xcc,0x00,0x20]
|
||||
// VI: v_mac_f16_e64 v0, -4.0, flat_scratch_lo ; encoding: [0x00,0x00,0x23,0xd1,0xf7,0xcc,0x00,0x00]
|
||||
|
||||
v_mac_f16_e64 v0, flat_scratch_lo, -4.0
|
||||
// NOSICI: error:
|
||||
// VI: v_mac_f16_e64 v0, flat_scratch_lo, -4.0 ; encoding: [0x00,0x00,0x23,0xd1,0x66,0xec,0x01,0x40]
|
||||
// VI: v_mac_f16_e64 v0, flat_scratch_lo, -4.0 ; encoding: [0x00,0x00,0x23,0xd1,0x66,0xee,0x01,0x00]
|
||||
|
||||
///===---------------------------------------------------------------------===//
|
||||
// VOP3 Instructions
|
||||
|
|
|
|||
|
|
@ -215,3 +215,9 @@
|
|||
|
||||
# VI: v_mad_f32 v9, 0.5, v5, -v8 ; encoding: [0x09,0x00,0xc1,0xd1,0xf0,0x0a,0x22,0x84]
|
||||
0x09 0x00 0xc1 0xd1 0xf0 0x0a 0x22 0x84
|
||||
|
||||
# VI: v_ceil_f32_e64 v0, neg(-1) ; encoding: [0x00,0x00,0x5d,0xd1,0xc1,0x00,0x00,0x20]
|
||||
0x00,0x00,0x5d,0xd1,0xc1,0x00,0x00,0x20
|
||||
|
||||
# VI: v_ceil_f32_e64 v0, neg(-1.0) ; encoding: [0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20]
|
||||
0x00,0x00,0x5d,0xd1,0xf3,0x00,0x00,0x20
|
||||
|
|
|
|||
Loading…
Reference in New Issue