forked from OSchip/llvm-project
[AArch64][SVE] Fix isel failure for FP-extending loads
DAGCombiner tries to combine a (fpext (load)) to (fround (extload)) but SVE has no FP-extending loads. By marking these as expand, the combine no longer happens. This also fixes a similar issue for fptrunc, where the source type is not a legal type. Reviewed By: bsmith, kmclaughlin Differential Revision: https://reviews.llvm.org/D102053
This commit is contained in:
Sander de Smalen
parent
ea64200b61
commit
407a33889d
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@ -1185,15 +1185,20 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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}
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}
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for (auto VT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32,
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MVT::nxv4f32, MVT::nxv2f64}) {
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for (auto InnerVT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16,
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MVT::nxv2f32, MVT::nxv4f32, MVT::nxv2f64}) {
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for (MVT VT : MVT::fp_scalable_vector_valuetypes()) {
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for (MVT InnerVT : MVT::fp_scalable_vector_valuetypes()) {
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// Avoid marking truncating FP stores as legal to prevent the
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// DAGCombiner from creating unsupported truncating stores.
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setTruncStoreAction(VT, InnerVT, Expand);
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// SVE does not have floating-point extending loads.
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setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
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setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
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setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
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}
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}
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for (auto VT : {MVT::nxv2f16, MVT::nxv4f16, MVT::nxv8f16, MVT::nxv2f32,
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MVT::nxv4f32, MVT::nxv2f64}) {
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setOperationAction(ISD::CONCAT_VECTORS, VT, Custom);
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setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom);
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setOperationAction(ISD::MGATHER, VT, Custom);
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@ -0,0 +1,85 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
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; fpext <vscale x 2 x half> -> <vscale x 2 x double>
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define <vscale x 2 x double> @ext2_f16_f64(<vscale x 2 x half> *%ptr, i64 %index) {
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; CHECK-LABEL: ext2_f16_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
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; CHECK-NEXT: fcvt z0.d, p0/m, z0.h
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; CHECK-NEXT: ret
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%load = load <vscale x 2 x half>, <vscale x 2 x half>* %ptr, align 4
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%load.ext = fpext <vscale x 2 x half> %load to <vscale x 2 x double>
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ret <vscale x 2 x double> %load.ext
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}
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; fpext <vscale x 4 x half> -> <vscale x 4 x double>
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define <vscale x 4 x double> @ext4_f16_f64(<vscale x 4 x half> *%ptr, i64 %index) {
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; CHECK-LABEL: ext4_f16_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: uunpklo z1.d, z0.s
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; CHECK-NEXT: uunpkhi z2.d, z0.s
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; CHECK-NEXT: fcvt z0.d, p0/m, z1.h
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; CHECK-NEXT: fcvt z1.d, p0/m, z2.h
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; CHECK-NEXT: ret
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%load = load <vscale x 4 x half>, <vscale x 4 x half>* %ptr, align 4
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%load.ext = fpext <vscale x 4 x half> %load to <vscale x 4 x double>
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ret <vscale x 4 x double> %load.ext
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}
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; fpext <vscale x 8 x half> -> <vscale x 8 x double>
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define <vscale x 8 x double> @ext8_f16_f64(<vscale x 8 x half> *%ptr, i64 %index) {
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; CHECK-LABEL: ext8_f16_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: uunpklo z1.s, z0.h
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; CHECK-NEXT: uunpkhi z0.s, z0.h
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; CHECK-NEXT: uunpklo z2.d, z1.s
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; CHECK-NEXT: uunpkhi z1.d, z1.s
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; CHECK-NEXT: uunpklo z3.d, z0.s
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; CHECK-NEXT: uunpkhi z4.d, z0.s
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; CHECK-NEXT: fcvt z0.d, p0/m, z2.h
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; CHECK-NEXT: fcvt z1.d, p0/m, z1.h
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; CHECK-NEXT: fcvt z2.d, p0/m, z3.h
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; CHECK-NEXT: fcvt z3.d, p0/m, z4.h
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; CHECK-NEXT: ret
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%load = load <vscale x 8 x half>, <vscale x 8 x half>* %ptr, align 4
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%load.ext = fpext <vscale x 8 x half> %load to <vscale x 8 x double>
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ret <vscale x 8 x double> %load.ext
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}
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; fpext <vscale x 2 x float> -> <vscale x 2 x double>
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define <vscale x 2 x double> @ext2_f32_f64(<vscale x 2 x float> *%ptr, i64 %index) {
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; CHECK-LABEL: ext2_f32_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
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; CHECK-NEXT: fcvt z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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%load = load <vscale x 2 x float>, <vscale x 2 x float>* %ptr, align 4
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%load.ext = fpext <vscale x 2 x float> %load to <vscale x 2 x double>
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ret <vscale x 2 x double> %load.ext
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}
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; fpext <vscale x 4 x float> -> <vscale x 4 x double>
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define <vscale x 4 x double> @ext4_f32_f64(<vscale x 4 x float> *%ptr, i64 %index) {
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; CHECK-LABEL: ext4_f32_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: uunpklo z1.d, z0.s
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; CHECK-NEXT: uunpkhi z2.d, z0.s
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; CHECK-NEXT: fcvt z0.d, p0/m, z1.s
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; CHECK-NEXT: fcvt z1.d, p0/m, z2.s
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; CHECK-NEXT: ret
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%load = load <vscale x 4 x float>, <vscale x 4 x float>* %ptr, align 4
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%load.ext = fpext <vscale x 4 x float> %load to <vscale x 4 x double>
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ret <vscale x 4 x double> %load.ext
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}
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@ -60,3 +60,28 @@ entry:
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store <vscale x 2 x half> %1, <vscale x 2 x half>* %dst, align 2
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ret void
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}
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define void @fptrunc8_f64_f16(<vscale x 8 x half> *%dst, <vscale x 8 x double> *%src) {
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; CHECK-LABEL: fptrunc8_f64_f16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x1]
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1, #1, mul vl]
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; CHECK-NEXT: ld1d { z2.d }, p0/z, [x1, #2, mul vl]
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; CHECK-NEXT: ld1d { z3.d }, p0/z, [x1, #3, mul vl]
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; CHECK-NEXT: fcvt z0.h, p0/m, z0.d
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; CHECK-NEXT: fcvt z1.h, p0/m, z1.d
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; CHECK-NEXT: fcvt z2.h, p0/m, z2.d
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; CHECK-NEXT: fcvt z3.h, p0/m, z3.d
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; CHECK-NEXT: uzp1 z2.s, z2.s, z3.s
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; CHECK-NEXT: uzp1 z0.s, z0.s, z1.s
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; CHECK-NEXT: uzp1 z0.h, z0.h, z2.h
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: st1h { z0.h }, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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%0 = load <vscale x 8 x double>, <vscale x 8 x double>* %src, align 8
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%1 = fptrunc <vscale x 8 x double> %0 to <vscale x 8 x half>
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store <vscale x 8 x half> %1, <vscale x 8 x half>* %dst, align 2
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ret void
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}
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