forked from OSchip/llvm-project
[PowerPC] Add vector conversion builtins to altivec.h - clang portion
This patch corresponds to review: https://reviews.llvm.org/D26308 It adds a number of vector type conversion builtins to altivec.h. llvm-svn: 286627
This commit is contained in:
Nemanja Ivanovic
parent
f1a12fe0f5
commit
4079fc8188
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@ -380,6 +380,16 @@ BUILTIN(__builtin_vsx_xvabsdp, "V2dV2d", "")
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BUILTIN(__builtin_vsx_xviexpdp, "V2dV2ULLiV2ULLi", "")
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BUILTIN(__builtin_vsx_xviexpsp, "V4fV4UiV4Ui", "")
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// Conversion builtins
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BUILTIN(__builtin_vsx_xvcvdpsxws, "V4SiV2d", "")
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BUILTIN(__builtin_vsx_xvcvdpuxws, "V4UiV2d", "")
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BUILTIN(__builtin_vsx_xvcvsxwdp, "V2dV4Si", "")
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BUILTIN(__builtin_vsx_xvcvuxwdp, "V2dV4Ui", "")
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BUILTIN(__builtin_vsx_xvcvspdp, "V2dV4f", "")
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BUILTIN(__builtin_vsx_xvcvsxdsp, "V4fV2SLLi", "")
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BUILTIN(__builtin_vsx_xvcvuxdsp, "V4fV2ULLi", "")
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BUILTIN(__builtin_vsx_xvcvdpsp, "V4fV2d", "")
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// HTM builtins
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BUILTIN(__builtin_tbegin, "UiUIi", "")
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BUILTIN(__builtin_tend, "UiUIi", "")
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@ -2732,20 +2732,284 @@ vec_vctuxs(vector float __a, int __b) {
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return __builtin_altivec_vctuxs(__a, __b);
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}
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/* vec_signed */
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static __inline__ vector signed int __ATTRS_o_ai
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vec_sld(vector signed int, vector signed int, unsigned const int __c);
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static __inline__ vector signed int __ATTRS_o_ai
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vec_signed(vector float __a) {
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return __builtin_convertvector(__a, vector signed int);
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}
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#ifdef __VSX__
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static __inline__ vector signed long long __ATTRS_o_ai
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vec_signed(vector double __a) {
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return __builtin_convertvector(__a, vector signed long long);
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}
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static __inline__ vector signed int __attribute__((__always_inline__))
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vec_signed2(vector double __a, vector double __b) {
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return (vector signed int) { __a[0], __a[1], __b[0], __b[1] };
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}
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static __inline__ vector signed int __ATTRS_o_ai
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vec_signede(vector double __a) {
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#ifdef __LITTLE_ENDIAN__
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vector signed int __ret = __builtin_vsx_xvcvdpsxws(__a);
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return vec_sld(__ret, __ret, 12);
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#else
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return __builtin_vsx_xvcvdpsxws(__a);
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#endif
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}
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static __inline__ vector signed int __ATTRS_o_ai
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vec_signedo(vector double __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvdpsxws(__a);
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#else
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vector signed int __ret = __builtin_vsx_xvcvdpsxws(__a);
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return vec_sld(__ret, __ret, 12);
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#endif
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}
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#endif
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/* vec_unsigned */
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static __inline__ vector unsigned int __ATTRS_o_ai
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vec_sld(vector unsigned int, vector unsigned int, unsigned const int __c);
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static __inline__ vector unsigned int __ATTRS_o_ai
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vec_unsigned(vector float __a) {
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return __builtin_convertvector(__a, vector unsigned int);
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}
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#ifdef __VSX__
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static __inline__ vector unsigned long long __ATTRS_o_ai
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vec_unsigned(vector double __a) {
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return __builtin_convertvector(__a, vector unsigned long long);
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}
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static __inline__ vector unsigned int __attribute__((__always_inline__))
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vec_unsigned2(vector double __a, vector double __b) {
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return (vector unsigned int) { __a[0], __a[1], __b[0], __b[1] };
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}
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static __inline__ vector unsigned int __ATTRS_o_ai
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vec_unsignede(vector double __a) {
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#ifdef __LITTLE_ENDIAN__
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vector unsigned int __ret = __builtin_vsx_xvcvdpuxws(__a);
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return vec_sld(__ret, __ret, 12);
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#else
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return __builtin_vsx_xvcvdpuxws(__a);
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#endif
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}
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static __inline__ vector unsigned int __ATTRS_o_ai
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vec_unsignedo(vector double __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvdpuxws(__a);
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#else
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vector unsigned int __ret = __builtin_vsx_xvcvdpuxws(__a);
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return vec_sld(__ret, __ret, 12);
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#endif
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}
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#endif
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/* vec_float */
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static __inline__ vector float __ATTRS_o_ai
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vec_sld(vector float, vector float, unsigned const int __c);
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static __inline__ vector float __ATTRS_o_ai
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vec_float(vector signed int __a) {
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return __builtin_convertvector(__a, vector float);
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}
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static __inline__ vector float __ATTRS_o_ai
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vec_float(vector unsigned int __a) {
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return __builtin_convertvector(__a, vector float);
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}
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#ifdef __VSX__
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static __inline__ vector float __ATTRS_o_ai
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vec_float2(vector signed long long __a, vector signed long long __b) {
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return (vector float) { __a[0], __a[1], __b[0], __b[1] };
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}
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static __inline__ vector float __ATTRS_o_ai
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vec_float2(vector unsigned long long __a, vector unsigned long long __b) {
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return (vector float) { __a[0], __a[1], __b[0], __b[1] };
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}
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static __inline__ vector float __ATTRS_o_ai
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vec_float2(vector double __a, vector double __b) {
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return (vector float) { __a[0], __a[1], __b[0], __b[1] };
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}
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static __inline__ vector float __ATTRS_o_ai
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vec_floate(vector signed long long __a) {
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#ifdef __LITTLE_ENDIAN__
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vector float __ret = __builtin_vsx_xvcvsxdsp(__a);
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return vec_sld(__ret, __ret, 12);
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#else
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return __builtin_vsx_xvcvsxdsp(__a);
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#endif
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}
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static __inline__ vector float __ATTRS_o_ai
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vec_floate(vector unsigned long long __a) {
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#ifdef __LITTLE_ENDIAN__
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vector float __ret = __builtin_vsx_xvcvuxdsp(__a);
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return vec_sld(__ret, __ret, 12);
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#else
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return __builtin_vsx_xvcvuxdsp(__a);
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#endif
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}
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static __inline__ vector float __ATTRS_o_ai
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vec_floate(vector double __a) {
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#ifdef __LITTLE_ENDIAN__
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vector float __ret = __builtin_vsx_xvcvdpsp(__a);
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return vec_sld(__ret, __ret, 12);
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#else
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return __builtin_vsx_xvcvdpsp(__a);
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#endif
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}
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static __inline__ vector float __ATTRS_o_ai
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vec_floato(vector signed long long __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvsxdsp(__a);
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#else
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vector float __ret = __builtin_vsx_xvcvsxdsp(__a);
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return vec_sld(__ret, __ret, 12);
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#endif
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}
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static __inline__ vector float __ATTRS_o_ai
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vec_floato(vector unsigned long long __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvuxdsp(__a);
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#else
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vector float __ret = __builtin_vsx_xvcvuxdsp(__a);
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return vec_sld(__ret, __ret, 12);
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#endif
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}
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static __inline__ vector float __ATTRS_o_ai
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vec_floato(vector double __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvdpsp(__a);
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#else
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vector float __ret = __builtin_vsx_xvcvdpsp(__a);
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return vec_sld(__ret, __ret, 12);
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#endif
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}
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#endif
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/* vec_double */
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#ifdef __VSX__
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static __inline__ vector double __ATTRS_o_ai
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vec_double(vector signed long long __a) {
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return __builtin_convertvector(__a, vector double);
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_double(vector unsigned long long __a) {
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return __builtin_convertvector(__a, vector double);
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doublee(vector signed int __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvsxwdp(vec_sld(__a, __a, 4));
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#else
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return __builtin_vsx_xvcvsxwdp(__a);
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#endif
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doublee(vector unsigned int __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvuxwdp(vec_sld(__a, __a, 4));
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#else
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return __builtin_vsx_xvcvuxwdp(__a);
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#endif
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doublee(vector float __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvspdp(vec_sld(__a, __a, 4));
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#else
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return __builtin_vsx_xvcvspdp(__a);
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#endif
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doubleh(vector signed int __a) {
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vector double __ret = {__a[0], __a[1]};
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return __ret;
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_double(vector unsigned long long __a) {
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vec_doubleh(vector unsigned int __a) {
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vector double __ret = {__a[0], __a[1]};
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return __ret;
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doubleh(vector float __a) {
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vector double __ret = {__a[0], __a[1]};
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return __ret;
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doublel(vector signed int __a) {
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vector double __ret = {__a[2], __a[3]};
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return __ret;
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doublel(vector unsigned int __a) {
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vector double __ret = {__a[2], __a[3]};
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return __ret;
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doublel(vector float __a) {
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vector double __ret = {__a[2], __a[3]};
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return __ret;
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doubleo(vector signed int __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvsxwdp(__a);
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#else
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return __builtin_vsx_xvcvsxwdp(vec_sld(__a, __a, 4));
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#endif
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doubleo(vector unsigned int __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvuxwdp(__a);
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#else
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return __builtin_vsx_xvcvuxwdp(vec_sld(__a, __a, 4));
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#endif
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}
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static __inline__ vector double __ATTRS_o_ai
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vec_doubleo(vector float __a) {
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#ifdef __LITTLE_ENDIAN__
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return __builtin_vsx_xvcvspdp(__a);
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#else
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return __builtin_vsx_xvcvspdp(vec_sld(__a, __a, 4));
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#endif
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}
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#endif
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/* vec_div */
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@ -1173,6 +1173,22 @@ void test6() {
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// CHECK: @llvm.ppc.altivec.vctuxs
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// CHECK-LE: @llvm.ppc.altivec.vctuxs
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res_vi = vec_signed(vf);
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// CHECK: fptosi <4 x float>
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// CHECK-LE: fptosi <4 x float>
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res_vui = vec_unsigned(vf);
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// CHECK: fptoui <4 x float>
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// CHECK-LE: fptoui <4 x float>
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res_vf = vec_float(vi);
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// CHECK: sitofp <4 x i32>
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// CHECK-LE: sitofp <4 x i32>
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res_vf = vec_float(vui);
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// CHECK: uitofp <4 x i32>
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// CHECK-LE: uitofp <4 x i32>
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/* vec_div */
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res_vsc = vec_div(vsc, vsc);
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// CHECK: sdiv <16 x i8>
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@ -210,15 +210,6 @@ void test1() {
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// CHECK-LE: call <2 x i64> @llvm.ppc.altivec.vcmpgtud(<2 x i64> %{{[0-9]*}}, <2 x i64> %{{[0-9]*}})
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// CHECK-PPC: error: call to 'vec_cmplt' is ambiguous
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/* vec_double */
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res_vd = vec_double(vsll);
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// CHECK: sitofp i64 {{.+}} to double
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// CHECK-BE: sitofp i64 {{.+}} to double
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res_vd = vec_double(vull);
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// CHECK: uitofp i64 {{.+}} to double
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// CHECK-BE: uitofp i64 {{.+}} to double
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/* vec_eqv */
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res_vsc = vec_eqv(vsc, vsc);
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// CHECK: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
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@ -1082,6 +1082,380 @@ void test1() {
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// CHECK-LE: uitofp <2 x i64> %{{.*}} to <2 x double>
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// CHECK-LE: fmul <2 x double>
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res_vsll = vec_signed(vd);
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// CHECK: fptosi <2 x double>
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// CHECK-LE: fptosi <2 x double>
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res_vsi = vec_signed2(vd, vd);
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// CHECK: extractelement <2 x double>
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// CHECK: fptosi double
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// CHECK: insertelement <4 x i32>
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// CHECK: extractelement <2 x double>
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// CHECK: fptosi double
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// CHECK: insertelement <4 x i32>
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// CHECK: extractelement <2 x double>
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// CHECK: fptosi double
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// CHECK: insertelement <4 x i32>
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// CHECK: extractelement <2 x double>
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// CHECK: fptosi double
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// CHECK: insertelement <4 x i32>
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// CHECK-LE: extractelement <2 x double>
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// CHECK-LE: fptosi double
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// CHECK-LE: insertelement <4 x i32>
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// CHECK-LE: extractelement <2 x double>
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// CHECK-LE: fptosi double
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// CHECK-LE: insertelement <4 x i32>
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// CHECK-LE: extractelement <2 x double>
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// CHECK-LE: fptosi double
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// CHECK-LE: insertelement <4 x i32>
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// CHECK-LE: extractelement <2 x double>
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// CHECK-LE: fptosi double
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// CHECK-LE: insertelement <4 x i32>
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res_vsi = vec_signede(vd);
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// CHECK: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
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// CHECK-LE: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
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// CHECK-LE: sub nsw i32 16
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// CHECK-LE: sub nsw i32 17
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// CHECK-LE: sub nsw i32 18
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// CHECK-LE: sub nsw i32 31
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// CHECK-LE: @llvm.ppc.altivec.vperm
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res_vsi = vec_signedo(vd);
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// CHECK: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
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// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
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// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
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// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
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// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
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// CHECK: @llvm.ppc.altivec.vperm
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// CHECK-LE: @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
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res_vull = vec_unsigned(vd);
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// CHECK: fptoui <2 x double>
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// CHECK-LE: fptoui <2 x double>
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res_vui = vec_unsigned2(vd, vd);
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// CHECK: extractelement <2 x double>
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// CHECK: fptoui double
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// CHECK: insertelement <4 x i32>
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// CHECK: extractelement <2 x double>
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// CHECK: fptoui double
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// CHECK: insertelement <4 x i32>
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// CHECK: extractelement <2 x double>
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// CHECK: fptoui double
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// CHECK: insertelement <4 x i32>
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// CHECK: extractelement <2 x double>
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// CHECK: fptoui double
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// CHECK: insertelement <4 x i32>
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// CHECK-LE: extractelement <2 x double>
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// CHECK-LE: fptoui double
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// CHECK-LE: insertelement <4 x i32>
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// CHECK-LE: extractelement <2 x double>
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// CHECK-LE: fptoui double
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// CHECK-LE: insertelement <4 x i32>
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// CHECK-LE: extractelement <2 x double>
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// CHECK-LE: fptoui double
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// CHECK-LE: insertelement <4 x i32>
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// CHECK-LE: extractelement <2 x double>
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// CHECK-LE: fptoui double
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// CHECK-LE: insertelement <4 x i32>
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|
||||
res_vui = vec_unsignede(vd);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
|
||||
// CHECK-LE: sub nsw i32 16
|
||||
// CHECK-LE: sub nsw i32 17
|
||||
// CHECK-LE: sub nsw i32 18
|
||||
// CHECK-LE: sub nsw i32 31
|
||||
// CHECK-LE: @llvm.ppc.altivec.vperm
|
||||
|
||||
res_vui = vec_unsignedo(vd);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
|
||||
// CHECK: @llvm.ppc.altivec.vperm
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
|
||||
|
||||
res_vf = vec_float2(vsll, vsll);
|
||||
// CHECK: extractelement <2 x i64>
|
||||
// CHECK: sitofp i64
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK: extractelement <2 x i64>
|
||||
// CHECK: sitofp i64
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK: extractelement <2 x i64>
|
||||
// CHECK: sitofp i64
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK: extractelement <2 x i64>
|
||||
// CHECK: sitofp i64
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x i64>
|
||||
// CHECK-LE: sitofp i64
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x i64>
|
||||
// CHECK-LE: sitofp i64
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x i64>
|
||||
// CHECK-LE: sitofp i64
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x i64>
|
||||
// CHECK-LE: sitofp i64
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
|
||||
res_vf = vec_float2(vull, vull);
|
||||
// CHECK: extractelement <2 x i64>
|
||||
// CHECK: uitofp i64
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK: extractelement <2 x i64>
|
||||
// CHECK: uitofp i64
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK: extractelement <2 x i64>
|
||||
// CHECK: uitofp i64
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK: extractelement <2 x i64>
|
||||
// CHECK: uitofp i64
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x i64>
|
||||
// CHECK-LE: uitofp i64
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x i64>
|
||||
// CHECK-LE: uitofp i64
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x i64>
|
||||
// CHECK-LE: uitofp i64
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x i64>
|
||||
// CHECK-LE: uitofp i64
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
|
||||
res_vf = vec_float2(vd, vd);
|
||||
// CHECK: extractelement <2 x double>
|
||||
// CHECK: fptrunc double
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK: extractelement <2 x double>
|
||||
// CHECK: fptrunc double
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK: extractelement <2 x double>
|
||||
// CHECK: fptrunc double
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK: extractelement <2 x double>
|
||||
// CHECK: fptrunc double
|
||||
// CHECK: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x double>
|
||||
// CHECK-LE: fptrunc double
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x double>
|
||||
// CHECK-LE: fptrunc double
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x double>
|
||||
// CHECK-LE: fptrunc double
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
// CHECK-LE: extractelement <2 x double>
|
||||
// CHECK-LE: fptrunc double
|
||||
// CHECK-LE: insertelement <4 x float>
|
||||
|
||||
res_vf = vec_floate(vsll);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvsxdsp
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvsxdsp
|
||||
// CHECK-LE: sub nsw i32 16
|
||||
// CHECK-LE: sub nsw i32 17
|
||||
// CHECK-LE: sub nsw i32 18
|
||||
// CHECK-LE: sub nsw i32 31
|
||||
// CHECK-LE: @llvm.ppc.altivec.vperm
|
||||
|
||||
res_vf = vec_floate(vull);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvuxdsp
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvuxdsp
|
||||
// CHECK-LE: sub nsw i32 16
|
||||
// CHECK-LE: sub nsw i32 17
|
||||
// CHECK-LE: sub nsw i32 18
|
||||
// CHECK-LE: sub nsw i32 31
|
||||
// CHECK-LE: @llvm.ppc.altivec.vperm
|
||||
|
||||
res_vf = vec_floate(vd);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvdpsp
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvdpsp
|
||||
// CHECK-LE: sub nsw i32 16
|
||||
// CHECK-LE: sub nsw i32 17
|
||||
// CHECK-LE: sub nsw i32 18
|
||||
// CHECK-LE: sub nsw i32 31
|
||||
// CHECK-LE: @llvm.ppc.altivec.vperm
|
||||
|
||||
res_vf = vec_floato(vsll);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvsxdsp
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
|
||||
// CHECK: @llvm.ppc.altivec.vperm
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvsxdsp
|
||||
|
||||
res_vf = vec_floato(vull);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvuxdsp
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
|
||||
// CHECK: @llvm.ppc.altivec.vperm
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvuxdsp
|
||||
|
||||
res_vf = vec_floato(vd);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvdpsp
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
|
||||
// CHECK: @llvm.ppc.altivec.vperm
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvdpsp
|
||||
|
||||
res_vd = vec_double(vsll);
|
||||
// CHECK: sitofp <2 x i64>
|
||||
// CHECK-LE: sitofp <2 x i64>
|
||||
|
||||
res_vd = vec_double(vull);
|
||||
// CHECK: uitofp <2 x i64>
|
||||
// CHECK-LE: uitofp <2 x i64>
|
||||
|
||||
res_vd = vec_doublee(vsi);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvsxwdp(<4 x i32
|
||||
// CHECK-LE: sub nsw i32 16
|
||||
// CHECK-LE: sub nsw i32 17
|
||||
// CHECK-LE: sub nsw i32 18
|
||||
// CHECK-LE: sub nsw i32 31
|
||||
// CHECK-LE: @llvm.ppc.altivec.vperm
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvsxwdp(<4 x i32
|
||||
|
||||
res_vd = vec_doublee(vui);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvuxwdp(<4 x i32
|
||||
// CHECK-LE: sub nsw i32 16
|
||||
// CHECK-LE: sub nsw i32 17
|
||||
// CHECK-LE: sub nsw i32 18
|
||||
// CHECK-LE: sub nsw i32 31
|
||||
// CHECK-LE: @llvm.ppc.altivec.vperm
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvuxwdp(<4 x i32
|
||||
|
||||
res_vd = vec_doublee(vf);
|
||||
// CHECK: @llvm.ppc.vsx.xvcvspdp(<4 x float
|
||||
// CHECK-LE: sub nsw i32 16
|
||||
// CHECK-LE: sub nsw i32 17
|
||||
// CHECK-LE: sub nsw i32 18
|
||||
// CHECK-LE: sub nsw i32 31
|
||||
// CHECK-LE: @llvm.ppc.altivec.vperm
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvspdp(<4 x float
|
||||
|
||||
res_vd = vec_doubleh(vsi);
|
||||
// CHECK: extractelement <4 x i32>
|
||||
// CHECK: sitofp i32
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK: extractelement <4 x i32>
|
||||
// CHECK: sitofp i32
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x i32>
|
||||
// CHECK-LE: sitofp i32
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x i32>
|
||||
// CHECK-LE: sitofp i32
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
|
||||
res_vd = vec_doubleh(vui);
|
||||
// CHECK: extractelement <4 x i32>
|
||||
// CHECK: uitofp i32
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK: extractelement <4 x i32>
|
||||
// CHECK: uitofp i32
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x i32>
|
||||
// CHECK-LE: uitofp i32
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x i32>
|
||||
// CHECK-LE: uitofp i32
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
|
||||
res_vd = vec_doubleh(vf);
|
||||
// CHECK: extractelement <4 x float>
|
||||
// CHECK: fpext float
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK: extractelement <4 x float>
|
||||
// CHECK: fpext float
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x float>
|
||||
// CHECK-LE: fpext float
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x float>
|
||||
// CHECK-LE: fpext float
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
|
||||
res_vd = vec_doublel(vsi);
|
||||
// CHECK: extractelement <4 x i32>
|
||||
// CHECK: sitofp i32
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK: extractelement <4 x i32>
|
||||
// CHECK: sitofp i32
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x i32>
|
||||
// CHECK-LE: sitofp i32
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x i32>
|
||||
// CHECK-LE: sitofp i32
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
|
||||
res_vd = vec_doublel(vui);
|
||||
// CHECK: extractelement <4 x i32>
|
||||
// CHECK: uitofp i32
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK: extractelement <4 x i32>
|
||||
// CHECK: uitofp i32
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x i32>
|
||||
// CHECK-LE: uitofp i32
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x i32>
|
||||
// CHECK-LE: uitofp i32
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
|
||||
res_vd = vec_doublel(vf);
|
||||
// CHECK: extractelement <4 x float>
|
||||
// CHECK: fpext float
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK: extractelement <4 x float>
|
||||
// CHECK: fpext float
|
||||
// CHECK: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x float>
|
||||
// CHECK-LE: fpext float
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
// CHECK-LE: extractelement <4 x float>
|
||||
// CHECK-LE: fpext float
|
||||
// CHECK-LE: insertelement <2 x double>
|
||||
|
||||
res_vd = vec_doubleo(vsi);
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
|
||||
// CHECK: @llvm.ppc.altivec.vperm
|
||||
// CHECK: @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvsxwdp(<4 x i32>
|
||||
|
||||
res_vd = vec_doubleo(vui);
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
|
||||
// CHECK: @llvm.ppc.altivec.vperm
|
||||
// CHECK: @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvuxwdp(<4 x i32>
|
||||
|
||||
res_vd = vec_doubleo(vf);
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 1
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 2
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 3
|
||||
// CHECK: add nsw i32 {{[0-9a-zA-Z%.]+}}, 15
|
||||
// CHECK: @llvm.ppc.altivec.vperm
|
||||
// CHECK: @llvm.ppc.vsx.xvcvspdp(<4 x float>
|
||||
// CHECK-LE: @llvm.ppc.vsx.xvcvspdp(<4 x float>
|
||||
|
||||
res_vbll = vec_reve(vbll);
|
||||
// CHECK: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK-LE: shufflevector <2 x i64> %{{[0-9]+}}, <2 x i64> %{{[0-9]+}}, <2 x i32> <i32 1, i32 0>
|
||||
|
|
|
|||
Loading…
Reference in New Issue