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[Bazel] Added missing targets to LLVM bazel rules. 

Added the following targets to the LLVM Bazel overlay:

AVR
Mips
MPS430
SystemZ
XCore

Reviewed By: GMNGeoffrey

Differential Revision: https://reviews.llvm.org/D106921
This commit is contained in:
Itai Zukerman 2021-07-28 13:27:05 -07:00 committed by Geoffrey Martin-Noble
parent 668aa531d6
commit 3ff451ca6a
2 changed files with 83 additions and 0 deletions
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5
utils/bazel/configure.bzl
View File

@ -16,15 +16,20 @@ DEFAULT_TARGETS = [
"AArch64",
"AMDGPU",
"ARM",
"AVR",
"BPF",
"Hexagon",
"Lanai",
"Mips",
"MSP430",
"NVPTX",
"PowerPC",
"RISCV",
"Sparc",
"SystemZ",
"WebAssembly",
"X86",
"XCore",
]
def _overlay_directories(repository_ctx):

78
utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
View File

@ -1506,6 +1506,21 @@ llvm_target_lib_list = [lib for lib in [
":r600_target_gen",
],
},
{
"name": "AVR",
"short_name": "AVR",
"tbl_outs": [
("-gen-asm-matcher", "lib/Target/AVR/AVRGenAsmMatcher.inc"),
("-gen-asm-writer", "lib/Target/AVR/AVRGenAsmWriter.inc"),
("-gen-callingconv", "lib/Target/AVR/AVRGenCallingConv.inc"),
("-gen-dag-isel", "lib/Target/AVR/AVRGenDAGISel.inc"),
("-gen-disassembler", "lib/Target/AVR/AVRGenDisassemblerTables.inc"),
("-gen-emitter", "lib/Target/AVR/AVRGenMCCodeEmitter.inc"),
("-gen-instr-info", "lib/Target/AVR/AVRGenInstrInfo.inc"),
("-gen-register-info", "lib/Target/AVR/AVRGenRegisterInfo.inc"),
("-gen-subtarget", "lib/Target/AVR/AVRGenSubtargetInfo.inc"),
],
},
{
"name": "BPF",
"short_name": "BPF",
@ -1552,6 +1567,41 @@ llvm_target_lib_list = [lib for lib in [
("-gen-subtarget", "lib/Target/Lanai/LanaiGenSubtargetInfo.inc"),
],
},
{
"name": "Mips",
"short_name": "Mips",
"tbl_outs": [
("-gen-asm-matcher", "lib/Target/Mips/MipsGenAsmMatcher.inc"),
("-gen-asm-writer", "lib/Target/Mips/MipsGenAsmWriter.inc"),
("-gen-callingconv", "lib/Target/Mips/MipsGenCallingConv.inc"),
("-gen-dag-isel", "lib/Target/Mips/MipsGenDAGISel.inc"),
("-gen-disassembler", "lib/Target/Mips/MipsGenDisassemblerTables.inc"),
("-gen-emitter", "lib/Target/Mips/MipsGenMCCodeEmitter.inc"),
("-gen-exegesis", "lib/Target/Mips/MipsGenExegesis.inc"),
("-gen-fast-isel", "lib/Target/Mips/MipsGenFastISel.inc"),
("-gen-global-isel", "lib/Target/Mips/MipsGenGlobalISel.inc"),
("-gen-instr-info", "lib/Target/Mips/MipsGenInstrInfo.inc"),
("-gen-pseudo-lowering", "lib/Target/Mips/MipsGenMCPseudoLowering.inc"),
("-gen-register-bank", "lib/Target/Mips/MipsGenRegisterBank.inc"),
("-gen-register-info", "lib/Target/Mips/MipsGenRegisterInfo.inc"),
("-gen-subtarget", "lib/Target/Mips/MipsGenSubtargetInfo.inc"),
],
},
{
"name": "MSP430",
"short_name": "MSP430",
"tbl_outs": [
("-gen-asm-matcher", "lib/Target/MSP430/MSP430GenAsmMatcher.inc"),
("-gen-asm-writer", "lib/Target/MSP430/MSP430GenAsmWriter.inc"),
("-gen-callingconv", "lib/Target/MSP430/MSP430GenCallingConv.inc"),
("-gen-dag-isel", "lib/Target/MSP430/MSP430GenDAGISel.inc"),
("-gen-disassembler", "lib/Target/MSP430/MSP430GenDisassemblerTables.inc"),
("-gen-emitter", "lib/Target/MSP430/MSP430GenMCCodeEmitter.inc"),
("-gen-instr-info", "lib/Target/MSP430/MSP430GenInstrInfo.inc"),
("-gen-register-info", "lib/Target/MSP430/MSP430GenRegisterInfo.inc"),
("-gen-subtarget", "lib/Target/MSP430/MSP430GenSubtargetInfo.inc"),
],
},
{
"name": "NVPTX",
"short_name": "NVPTX",
@ -1596,6 +1646,21 @@ llvm_target_lib_list = [lib for lib in [
("-gen-disassembler", "lib/Target/Sparc/SparcGenDisassemblerTables.inc"),
],
},
{
"name": "SystemZ",
"short_name": "SystemZ",
"tbl_outs": [
("-gen-asm-matcher", "lib/Target/SystemZ/SystemZGenAsmMatcher.inc"),
("-gen-asm-writer", "lib/Target/SystemZ/SystemZGenAsmWriter.inc"),
("-gen-callingconv", "lib/Target/SystemZ/SystemZGenCallingConv.inc"),
("-gen-dag-isel", "lib/Target/SystemZ/SystemZGenDAGISel.inc"),
("-gen-disassembler", "lib/Target/SystemZ/SystemZGenDisassemblerTables.inc"),
("-gen-emitter", "lib/Target/SystemZ/SystemZGenMCCodeEmitter.inc"),
("-gen-instr-info", "lib/Target/SystemZ/SystemZGenInstrInfo.inc"),
("-gen-register-info", "lib/Target/SystemZ/SystemZGenRegisterInfo.inc"),
("-gen-subtarget", "lib/Target/SystemZ/SystemZGenSubtargetInfo.inc"),
],
},
{
"name": "RISCV",
"short_name": "RISCV",
@ -1650,6 +1715,19 @@ llvm_target_lib_list = [lib for lib in [
("-gen-exegesis", "lib/Target/X86/X86GenExegesis.inc"),
],
},
{
"name": "XCore",
"short_name": "XCore",
"tbl_outs": [
("-gen-asm-writer", "lib/Target/XCore/XCoreGenAsmWriter.inc"),
("-gen-callingconv", "lib/Target/XCore/XCoreGenCallingConv.inc"),
("-gen-dag-isel", "lib/Target/XCore/XCoreGenDAGISel.inc"),
("-gen-disassembler", "lib/Target/XCore/XCoreGenDisassemblerTables.inc"),
("-gen-instr-info", "lib/Target/XCore/XCoreGenInstrInfo.inc"),
("-gen-register-info", "lib/Target/XCore/XCoreGenRegisterInfo.inc"),
("-gen-subtarget", "lib/Target/XCore/XCoreGenSubtargetInfo.inc"),
],
},
] if lib["name"] in llvm_targets]
cc_library(