forked from OSchip/llvm-project
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bc4679335c
commit
3fec5ff14b
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@ -2488,44 +2488,46 @@ def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
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class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, itin, opc, asm, pattern> {
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: T2ThreeReg<oops, iops, itin, opc, asm, pattern> {
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let Inst{31-27} = 0b11111;
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let Inst{26-22} = 0b01010;
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let Inst{21-20} = op1;
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let Inst{15-12} = 0b1111;
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let Inst{7-6} = 0b10;
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let Inst{5-4} = op2;
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let Rn{3-0} = Rm{3-0};
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}
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def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
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"clz", "\t$dst, $src", [(set rGPR:$dst, (ctlz rGPR:$src))]>;
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def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
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"clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>;
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def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
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"rbit", "\t$dst, $src",
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[(set rGPR:$dst, (ARMrbit rGPR:$src))]>;
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def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
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"rbit", "\t$Rd, $Rm",
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[(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>;
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def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
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"rev", ".w\t$dst, $src", [(set rGPR:$dst, (bswap rGPR:$src))]>;
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def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
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"rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>;
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def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
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"rev16", ".w\t$dst, $src",
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[(set rGPR:$dst,
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(or (and (srl rGPR:$src, (i32 8)), 0xFF),
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(or (and (shl rGPR:$src, (i32 8)), 0xFF00),
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(or (and (srl rGPR:$src, (i32 8)), 0xFF0000),
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(and (shl rGPR:$src, (i32 8)), 0xFF000000)))))]>;
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def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
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"rev16", ".w\t$Rd, $Rm",
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[(set rGPR:$Rd,
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(or (and (srl rGPR:$Rm, (i32 8)), 0xFF),
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(or (and (shl rGPR:$Rm, (i32 8)), 0xFF00),
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(or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
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(and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
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def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$dst), (ins rGPR:$src), IIC_iUNAr,
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"revsh", ".w\t$dst, $src",
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[(set rGPR:$dst,
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def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
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"revsh", ".w\t$Rd, $Rm",
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[(set rGPR:$Rd,
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(sext_inreg
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(or (srl (and rGPR:$src, 0xFF00), (i32 8)),
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(shl rGPR:$src, (i32 8))), i16))]>;
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(or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
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(shl rGPR:$Rm, (i32 8))), i16))]>;
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def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
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IIC_iBITsi, "pkhbt", "\t$dst, $src1, $src2$sh",
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[(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF),
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(and (shl rGPR:$src2, lsl_amt:$sh),
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def t2PKHBT : T2ThreeReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
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IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",
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[(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF),
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(and (shl rGPR:$Rm, lsl_amt:$sh),
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0xFFFF0000)))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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let Inst{31-27} = 0b11101;
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@ -2533,6 +2535,10 @@ def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
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let Inst{24-20} = 0b01100;
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let Inst{5} = 0; // BT form
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let Inst{4} = 0;
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bits<5> sh;
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let Inst{14-12} = sh{4-2};
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let Inst{7-6} = sh{1-0};
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}
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// Alternate cases for PKHBT where identities eliminate some nodes.
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@ -2545,10 +2551,11 @@ def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
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// Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
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// will match the pattern below.
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def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
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IIC_iBITsi, "pkhtb", "\t$dst, $src1, $src2$sh",
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[(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
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(and (sra rGPR:$src2, asr_amt:$sh),
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def t2PKHTB : T2ThreeReg<
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(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
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IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh",
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[(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000),
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(and (sra rGPR:$Rm, asr_amt:$sh),
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0xFFFF)))]>,
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Requires<[HasT2ExtractPack, IsThumb2]> {
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let Inst{31-27} = 0b11101;
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@ -2556,6 +2563,10 @@ def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
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let Inst{24-20} = 0b01100;
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let Inst{5} = 1; // TB form
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let Inst{4} = 0;
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bits<5> sh;
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let Inst{14-12} = sh{4-2};
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let Inst{7-6} = sh{1-0};
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}
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// Alternate cases for PKHTB where identities eliminate some nodes. Note that
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@ -71,3 +71,27 @@
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@ CHECK: smlabt r0, r1, r2, r0 @ encoding: [0xc1,0x02,0x00,0xe1]
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smlabt r0, r1, r2, r0
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@ CHECK: clz r0, r0 @ encoding: [0x10,0x0f,0x6f,0xe1]
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clz r0, r0
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@ CHECK: rev r0, r0 @ encoding: [0x30,0x0f,0xbf,0xe6]
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rev r0, r0
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@ CHECK: revsh r0, r0 @ encoding: [0xb0,0x0f,0xff,0xe6]
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revsh r0, r0
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@ CHECK: pkhbt r0, r0, r1, lsl #16 @ encoding: [0x11,0x08,0x80,0xe6]
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pkhbt r0, r0, r1, lsl #16
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@ CHECK: pkhbt r0, r0, r1, lsl #12 @ encoding: [0x11,0x06,0x80,0xe6]
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pkhbt r0, r0, r1, lsl #16
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@ CHECK: pkhbt r0, r0, r1, lsl #18 @ encoding: [0x11,0x09,0x80,0xe6]
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pkhbt r0, r0, r1, lsl #18
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@ CHECK: pkhbt r0, r0, r1 @ encoding: [0x11,0x00,0x80,0xe6]
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pkhbt r0, r0, r1
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@ CHECK: pkhtb r0, r0, r1, asr #16 @ encoding: [0x51,0x08,0x80,0xe6]
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pkhtb r0, r0, r1, asr #16
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@ CHECK: pkhtb r0, r0, r1, asr #12 @ encoding: [0x51,0x06,0x80,0xe6]
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pkhtb r0, r0, r1, asr #12
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@ CHECK: pkhtb r0, r0, r1, asr #18 @ encoding: [0x51,0x09,0x80,0xe6]
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pkhtb r0, r0, r1, asr #18
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@ CHECK: pkhtb r0, r0, r1, asr #22 @ encoding: [0x51,0x0b,0x80,0xe6]
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pkhtb r0, r0, r1, asr #22
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