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[AArch64] Fix the ordering of the accumulate operand in SchedRW list. 

Patch by Dave Estes <cestes@codeaurora.org>
http://reviews.llvm.org/D4037

llvm-svn: 210446
This commit is contained in:
Chad Rosier 2014-06-09 01:54:00 +00:00
parent d96e9f14ee
commit 3fe0c876c4
2 changed files with 7 additions and 6 deletions
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6
llvm/lib/Target/AArch64/AArch64InstrFormats.td
View File

@ -1323,13 +1323,13 @@ class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
multiclass MulAccum<bit isSub, string asm, SDNode AccNode> { multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm, def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
[(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))]>, [(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))]>,
Sched<[WriteIM32, ReadIMA, ReadIM, ReadIM]> { Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
let Inst{31} = 0; let Inst{31} = 0;
} }
def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm, def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
[(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))]>, [(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))]>,
Sched<[WriteIM64, ReadIMA, ReadIM, ReadIM]> { Sched<[WriteIM64, ReadIM, ReadIM, ReadIMA]> {
let Inst{31} = 1; let Inst{31} = 1;
} }
} }
@ -1339,7 +1339,7 @@ class WideMulAccum<bit isSub, bits<3> opc, string asm,
: BaseMulAccum<isSub, opc, GPR32, GPR64, asm, : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
[(set GPR64:$Rd, (AccNode GPR64:$Ra, [(set GPR64:$Rd, (AccNode GPR64:$Ra,
(mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>, (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
Sched<[WriteIM32, ReadIMA, ReadIM, ReadIM]> { Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
let Inst{31} = 1; let Inst{31} = 1;
} }

7
llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll
View File

@ -6,9 +6,10 @@
; ;
; CHECK: ********** MI Scheduling ********** ; CHECK: ********** MI Scheduling **********
; CHECK: shiftable ; CHECK: shiftable
; CHECK: *** Final schedule for BB#0 *** ; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0
; CHECK: ADDXrr %vreg0, %vreg2 ; CHECK: Successors:
; CHECK: ADDXrs %vreg0, %vreg2, 5 ; CHECK-NEXT: val SU(4): Latency=1 Reg=%vreg2
; CHECK-NEXT: val SU(3): Latency=2 Reg=%vreg2
; CHECK: ********** INTERVALS ********** ; CHECK: ********** INTERVALS **********
define i64 @shiftable(i64 %A, i64 %B) { define i64 @shiftable(i64 %A, i64 %B) {
%tmp0 = sub i64 %B, 20 %tmp0 = sub i64 %B, 20