forked from OSchip/llvm-project
Generalize instcombine's support for combining multiple bit checks into a single test. Patch by Dirk Steinke!
llvm-svn: 113423
This commit is contained in:
Owen Anderson
parent
8ead237758
commit
3fe002dfb5
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@ -434,6 +434,270 @@ Value *InstCombiner::FoldLogicalPlusAnd(Value *LHS, Value *RHS,
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return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold");
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return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold");
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}
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}
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/// enum for classifying (icmp eq (A & B), C) and (icmp ne (A & B), C)
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/// One of A and B is considered the mask, the other the value. This is
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/// described as the "AMask" or "BMask" part of the enum. If the enum
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/// contains only "Mask", then both A and B can be considered masks.
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/// If A is the mask, then it was proven, that (A & C) == C. This
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/// is trivial if C == A, or C == 0. If both A and C are constants, this
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/// proof is also easy.
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/// For the following explanations we assume that A is the mask.
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/// The part "AllOnes" declares, that the comparison is true only
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/// if (A & B) == A, or all bits of A are set in B.
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/// Example: (icmp eq (A & 3), 3) -> FoldMskICmp_AMask_AllOnes
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/// The part "AllZeroes" declares, that the comparison is true only
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/// if (A & B) == 0, or all bits of A are cleared in B.
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/// Example: (icmp eq (A & 3), 0) -> FoldMskICmp_Mask_AllZeroes
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/// The part "Mixed" declares, that (A & B) == C and C might or might not
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/// contain any number of one bits and zero bits.
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/// Example: (icmp eq (A & 3), 1) -> FoldMskICmp_AMask_Mixed
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/// The Part "Not" means, that in above descriptions "==" should be replaced
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/// by "!=".
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/// Example: (icmp ne (A & 3), 3) -> FoldMskICmp_AMask_NotAllOnes
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/// If the mask A contains a single bit, then the following is equivalent:
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/// (icmp eq (A & B), A) equals (icmp ne (A & B), 0)
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/// (icmp ne (A & B), A) equals (icmp eq (A & B), 0)
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enum MaskedICmpType {
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FoldMskICmp_AMask_AllOnes = 1,
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FoldMskICmp_AMask_NotAllOnes = 2,
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FoldMskICmp_BMask_AllOnes = 4,
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FoldMskICmp_BMask_NotAllOnes = 8,
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FoldMskICmp_Mask_AllZeroes = 16,
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FoldMskICmp_Mask_NotAllZeroes = 32,
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FoldMskICmp_AMask_Mixed = 64,
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FoldMskICmp_AMask_NotMixed = 128,
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FoldMskICmp_BMask_Mixed = 256,
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FoldMskICmp_BMask_NotMixed = 512
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};
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/// return the set of pattern classes (from MaskedICmpType)
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/// that (icmp SCC (A & B), C) satisfies
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static unsigned getTypeOfMaskedICmp(Value* A, Value* B, Value* C,
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ICmpInst::Predicate SCC)
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{
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ConstantInt *ACst = dyn_cast<ConstantInt>(A);
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ConstantInt *BCst = dyn_cast<ConstantInt>(B);
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ConstantInt *CCst = dyn_cast<ConstantInt>(C);
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bool icmp_eq = (SCC == ICmpInst::ICMP_EQ);
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bool icmp_abit = (ACst != 0 && !ACst->isZero() &&
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ACst->getValue().isPowerOf2());
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bool icmp_bbit = (BCst != 0 && !BCst->isZero() &&
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BCst->getValue().isPowerOf2());
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unsigned result = 0;
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if (CCst != 0 && CCst->isZero()) {
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// if C is zero, then both A and B qualify as mask
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result |= (icmp_eq ? (FoldMskICmp_Mask_AllZeroes |
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FoldMskICmp_Mask_AllZeroes |
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FoldMskICmp_AMask_Mixed |
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FoldMskICmp_BMask_Mixed)
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: (FoldMskICmp_Mask_NotAllZeroes |
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FoldMskICmp_Mask_NotAllZeroes |
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FoldMskICmp_AMask_NotMixed |
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FoldMskICmp_BMask_NotMixed));
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if (icmp_abit)
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result |= (icmp_eq ? (FoldMskICmp_AMask_NotAllOnes |
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FoldMskICmp_AMask_NotMixed)
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: (FoldMskICmp_AMask_AllOnes |
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FoldMskICmp_AMask_Mixed));
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if (icmp_bbit)
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result |= (icmp_eq ? (FoldMskICmp_BMask_NotAllOnes |
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FoldMskICmp_BMask_NotMixed)
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: (FoldMskICmp_BMask_AllOnes |
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FoldMskICmp_BMask_Mixed));
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return result;
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}
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if (A == C) {
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result |= (icmp_eq ? (FoldMskICmp_AMask_AllOnes |
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FoldMskICmp_AMask_Mixed)
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: (FoldMskICmp_AMask_NotAllOnes |
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FoldMskICmp_AMask_NotMixed));
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if (icmp_abit)
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result |= (icmp_eq ? (FoldMskICmp_Mask_NotAllZeroes |
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FoldMskICmp_AMask_NotMixed)
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: (FoldMskICmp_Mask_AllZeroes |
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FoldMskICmp_AMask_Mixed));
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}
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else if (ACst != 0 && CCst != 0 &&
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ConstantExpr::getAnd(ACst, CCst) == CCst) {
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result |= (icmp_eq ? FoldMskICmp_AMask_Mixed
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: FoldMskICmp_AMask_NotMixed);
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}
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if (B == C)
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{
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result |= (icmp_eq ? (FoldMskICmp_BMask_AllOnes |
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FoldMskICmp_BMask_Mixed)
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: (FoldMskICmp_BMask_NotAllOnes |
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FoldMskICmp_BMask_NotMixed));
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if (icmp_bbit)
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result |= (icmp_eq ? (FoldMskICmp_Mask_NotAllZeroes |
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FoldMskICmp_BMask_NotMixed)
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: (FoldMskICmp_Mask_AllZeroes |
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FoldMskICmp_BMask_Mixed));
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}
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else if (BCst != 0 && CCst != 0 &&
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ConstantExpr::getAnd(BCst, CCst) == CCst) {
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result |= (icmp_eq ? FoldMskICmp_BMask_Mixed
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: FoldMskICmp_BMask_NotMixed);
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}
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return result;
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}
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/// foldLogOpOfMaskedICmpsHelper:
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/// handle (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E)
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/// return the set of pattern classes (from MaskedICmpType)
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/// that both LHS and RHS satisfy
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static unsigned foldLogOpOfMaskedICmpsHelper(Value*& A,
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Value*& B, Value*& C,
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Value*& D, Value*& E,
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ICmpInst *LHS, ICmpInst *RHS) {
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ICmpInst::Predicate LHSCC = LHS->getPredicate(), RHSCC = RHS->getPredicate();
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if (LHSCC != ICmpInst::ICMP_EQ && LHSCC != ICmpInst::ICMP_NE) return 0;
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if (RHSCC != ICmpInst::ICMP_EQ && RHSCC != ICmpInst::ICMP_NE) return 0;
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if (LHS->getOperand(0)->getType() != RHS->getOperand(0)->getType()) return 0;
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// vectors are not (yet?) supported
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if (LHS->getOperand(0)->getType()->isVectorTy()) return 0;
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// Here comes the tricky part:
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// LHS might be of the form L11 & L12 == X, X == L21 & L22,
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// and L11 & L12 == L21 & L22. The same goes for RHS.
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// Now we must find those components L** and R**, that are equal, so
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// that we can extract the parameters A, B, C, D, and E for the canonical
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// above.
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Value *L1 = LHS->getOperand(0);
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Value *L2 = LHS->getOperand(1);
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Value *L11,*L12,*L21,*L22;
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if (match(L1, m_And(m_Value(L11), m_Value(L12)))) {
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if (!match(L2, m_And(m_Value(L21), m_Value(L22))))
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L21 = L22 = 0;
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}
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else {
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if (!match(L2, m_And(m_Value(L11), m_Value(L12))))
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return 0;
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std::swap(L1, L2);
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L21 = L22 = 0;
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}
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Value *R1 = RHS->getOperand(0);
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Value *R2 = RHS->getOperand(1);
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Value *R11,*R12;
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bool ok = false;
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if (match(R1, m_And(m_Value(R11), m_Value(R12)))) {
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if (R11 != 0 && (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22)) {
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A = R11; D = R12; E = R2; ok = true;
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}
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else
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if (R12 != 0 && (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22)) {
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A = R12; D = R11; E = R2; ok = true;
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}
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}
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if (!ok && match(R2, m_And(m_Value(R11), m_Value(R12)))) {
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if (R11 != 0 && (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22)) {
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A = R11; D = R12; E = R1; ok = true;
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}
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else
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if (R12 != 0 && (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22)) {
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A = R12; D = R11; E = R1; ok = true;
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}
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else
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return 0;
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}
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if (!ok)
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return 0;
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if (L11 == A) {
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B = L12; C = L2;
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}
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else if (L12 == A) {
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B = L11; C = L2;
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}
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else if (L21 == A) {
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B = L22; C = L1;
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}
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else if (L22 == A) {
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B = L21; C = L1;
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}
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unsigned left_type = getTypeOfMaskedICmp(A, B, C, LHSCC);
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unsigned right_type = getTypeOfMaskedICmp(A, D, E, RHSCC);
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return left_type & right_type;
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}
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/// foldLogOpOfMaskedICmps:
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/// try to fold (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E)
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/// into a single (icmp(A & X) ==/!= Y)
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static Value* foldLogOpOfMaskedICmps(ICmpInst *LHS, ICmpInst *RHS,
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ICmpInst::Predicate NEWCC,
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llvm::InstCombiner::BuilderTy* Builder) {
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Value *A = 0, *B = 0, *C = 0, *D = 0, *E = 0;
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unsigned mask = foldLogOpOfMaskedICmpsHelper(A, B, C, D, E, LHS, RHS);
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if (mask == 0) return 0;
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if (NEWCC == ICmpInst::ICMP_NE)
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mask >>= 1; // treat "Not"-states as normal states
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if (mask & FoldMskICmp_Mask_AllZeroes) {
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// (icmp eq (A & B), 0) & (icmp eq (A & D), 0)
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// -> (icmp eq (A & (B|D)), 0)
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Value* newOr = Builder->CreateOr(B, D);
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Value* newAnd = Builder->CreateAnd(A, newOr);
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// we can't use C as zero, because we might actually handle
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// (icmp ne (A & B), B) & (icmp ne (A & D), D)
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// with B and D, having a single bit set
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Value* zero = Constant::getNullValue(A->getType());
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return Builder->CreateICmp(NEWCC, newAnd, zero);
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}
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else if (mask & FoldMskICmp_BMask_AllOnes) {
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// (icmp eq (A & B), B) & (icmp eq (A & D), D)
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// -> (icmp eq (A & (B|D)), (B|D))
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Value* newOr = Builder->CreateOr(B, D);
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Value* newAnd = Builder->CreateAnd(A, newOr);
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return Builder->CreateICmp(NEWCC, newAnd, newOr);
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}
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else if (mask & FoldMskICmp_AMask_AllOnes) {
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// (icmp eq (A & B), A) & (icmp eq (A & D), A)
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// -> (icmp eq (A & (B&D)), A)
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Value* newAnd1 = Builder->CreateAnd(B, D);
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Value* newAnd = Builder->CreateAnd(A, newAnd1);
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return Builder->CreateICmp(NEWCC, newAnd, A);
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}
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else if (mask & FoldMskICmp_BMask_Mixed) {
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// (icmp eq (A & B), C) & (icmp eq (A & D), E)
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// We already know that B & C == C && D & E == E.
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// If we can prove that (B & D) & (C ^ E) == 0, that is, the bits of
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// C and E, which are shared by both the mask B and the mask D, don't
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// contradict, then we can transform to
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// -> (icmp eq (A & (B|D)), (C|E))
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// Currently, we only handle the case of B, C, D, and E being constant.
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ConstantInt *BCst = dyn_cast<ConstantInt>(B);
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if (BCst == 0) return 0;
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ConstantInt *DCst = dyn_cast<ConstantInt>(D);
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if (DCst == 0) return 0;
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// we can't simply use C and E, because we might actually handle
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// (icmp ne (A & B), B) & (icmp eq (A & D), D)
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// with B and D, having a single bit set
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ConstantInt *CCst = dyn_cast<ConstantInt>(C);
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if (CCst == 0) return 0;
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if (LHS->getPredicate() != NEWCC)
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CCst = dyn_cast<ConstantInt>( ConstantExpr::getXor(BCst, CCst) );
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ConstantInt *ECst = dyn_cast<ConstantInt>(E);
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if (ECst == 0) return 0;
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if (RHS->getPredicate() != NEWCC)
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ECst = dyn_cast<ConstantInt>( ConstantExpr::getXor(DCst, ECst) );
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ConstantInt* MCst = dyn_cast<ConstantInt>(
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ConstantExpr::getAnd(ConstantExpr::getAnd(BCst, DCst),
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ConstantExpr::getXor(CCst, ECst)) );
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// if there is a conflict we should actually return a false for the
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// whole construct
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if (!MCst->isZero())
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return 0;
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Value* newOr1 = Builder->CreateOr(B, D);
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Value* newOr2 = ConstantExpr::getOr(CCst, ECst);
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Value* newAnd = Builder->CreateAnd(A, newOr1);
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return Builder->CreateICmp(NEWCC, newAnd, newOr2);
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}
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return 0;
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}
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/// FoldAndOfICmps - Fold (icmp)&(icmp) if possible.
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/// FoldAndOfICmps - Fold (icmp)&(icmp) if possible.
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Value *InstCombiner::FoldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS) {
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Value *InstCombiner::FoldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS) {
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ICmpInst::Predicate LHSCC = LHS->getPredicate(), RHSCC = RHS->getPredicate();
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ICmpInst::Predicate LHSCC = LHS->getPredicate(), RHSCC = RHS->getPredicate();
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@ -451,6 +715,13 @@ Value *InstCombiner::FoldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS) {
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return getICmpValue(isSigned, Code, Op0, Op1, Builder);
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return getICmpValue(isSigned, Code, Op0, Op1, Builder);
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}
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}
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}
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}
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{
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// handle (roughly):
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// (icmp eq (A & B), C) & (icmp eq (A & D), E)
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Value* fold = foldLogOpOfMaskedICmps(LHS, RHS, ICmpInst::ICMP_EQ, Builder);
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if (fold) return fold;
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}
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// This only handles icmp of constants: (icmp1 A, C1) & (icmp2 B, C2).
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// This only handles icmp of constants: (icmp1 A, C1) & (icmp2 B, C2).
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Value *Val = LHS->getOperand(0), *Val2 = RHS->getOperand(0);
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Value *Val = LHS->getOperand(0), *Val2 = RHS->getOperand(0);
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@ -472,22 +743,6 @@ Value *InstCombiner::FoldAndOfICmps(ICmpInst *LHS, ICmpInst *RHS) {
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Value *NewOr = Builder->CreateOr(Val, Val2);
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Value *NewOr = Builder->CreateOr(Val, Val2);
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return Builder->CreateICmp(LHSCC, NewOr, LHSCst);
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return Builder->CreateICmp(LHSCC, NewOr, LHSCst);
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}
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}
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// (icmp ne (A & C1), 0) & (icmp ne (A & C2), 0) -->
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// (icmp eq (A & (C1|C2)), (C1|C2)) where C1 and C2 are non-zero POT
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if (LHSCC == ICmpInst::ICMP_NE && LHSCst->isZero()) {
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|
||||||
Value *Op1 = 0, *Op2 = 0;
|
|
||||||
ConstantInt *CI1 = 0, *CI2 = 0;
|
|
||||||
if (match(LHS->getOperand(0), m_And(m_Value(Op1), m_ConstantInt(CI1))) &&
|
|
||||||
match(RHS->getOperand(0), m_And(m_Value(Op2), m_ConstantInt(CI2)))) {
|
|
||||||
if (Op1 == Op2 && !CI1->isZero() && !CI2->isZero() &&
|
|
||||||
CI1->getValue().isPowerOf2() && CI2->getValue().isPowerOf2()) {
|
|
||||||
Constant *ConstOr = ConstantExpr::getOr(CI1, CI2);
|
|
||||||
Value *NewAnd = Builder->CreateAnd(Op1, ConstOr);
|
|
||||||
return Builder->CreateICmp(ICmpInst::ICMP_EQ, NewAnd, ConstOr);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// From here on, we only handle:
|
// From here on, we only handle:
|
||||||
|
|
@ -1161,6 +1416,13 @@ Value *InstCombiner::FoldOrOfICmps(ICmpInst *LHS, ICmpInst *RHS) {
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
{
|
||||||
|
// handle (roughly):
|
||||||
|
// (icmp ne (A & B), C) | (icmp ne (A & D), E)
|
||||||
|
Value* fold = foldLogOpOfMaskedICmps(LHS, RHS, ICmpInst::ICMP_NE, Builder);
|
||||||
|
if (fold) return fold;
|
||||||
|
}
|
||||||
|
|
||||||
// This only handles icmp of constants: (icmp1 A, C1) | (icmp2 B, C2).
|
// This only handles icmp of constants: (icmp1 A, C1) | (icmp2 B, C2).
|
||||||
Value *Val = LHS->getOperand(0), *Val2 = RHS->getOperand(0);
|
Value *Val = LHS->getOperand(0), *Val2 = RHS->getOperand(0);
|
||||||
ConstantInt *LHSCst = dyn_cast<ConstantInt>(LHS->getOperand(1));
|
ConstantInt *LHSCst = dyn_cast<ConstantInt>(LHS->getOperand(1));
|
||||||
|
|
@ -1173,22 +1435,6 @@ Value *InstCombiner::FoldOrOfICmps(ICmpInst *LHS, ICmpInst *RHS) {
|
||||||
Value *NewOr = Builder->CreateOr(Val, Val2);
|
Value *NewOr = Builder->CreateOr(Val, Val2);
|
||||||
return Builder->CreateICmp(LHSCC, NewOr, LHSCst);
|
return Builder->CreateICmp(LHSCC, NewOr, LHSCst);
|
||||||
}
|
}
|
||||||
|
|
||||||
// (icmp eq (A & C1), 0) | (icmp eq (A & C2), 0) -->
|
|
||||||
// (icmp ne (A & (C1|C2)), (C1|C2)) where C1 and C2 are non-zero POT
|
|
||||||
if (LHSCC == ICmpInst::ICMP_EQ && LHSCst->isZero()) {
|
|
||||||
Value *Op1 = 0, *Op2 = 0;
|
|
||||||
ConstantInt *CI1 = 0, *CI2 = 0;
|
|
||||||
if (match(LHS->getOperand(0), m_And(m_Value(Op1), m_ConstantInt(CI1))) &&
|
|
||||||
match(RHS->getOperand(0), m_And(m_Value(Op2), m_ConstantInt(CI2)))) {
|
|
||||||
if (Op1 == Op2 && !CI1->isZero() && !CI2->isZero() &&
|
|
||||||
CI1->getValue().isPowerOf2() && CI2->getValue().isPowerOf2()) {
|
|
||||||
Constant *ConstOr = ConstantExpr::getOr(CI1, CI2);
|
|
||||||
Value *NewAnd = Builder->CreateAnd(Op1, ConstOr);
|
|
||||||
return Builder->CreateICmp(ICmpInst::ICMP_NE, NewAnd, ConstOr);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// From here on, we only handle:
|
// From here on, we only handle:
|
||||||
|
|
|
||||||
|
|
@ -23,4 +23,350 @@ entry:
|
||||||
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
ret i32 %storemerge
|
ret i32 %storemerge
|
||||||
}
|
}
|
||||||
|
|
||||||
|
; tests to check combining (icmp eq (A & B), C) & (icmp eq (A & D), E)
|
||||||
|
; tests to check if (icmp eq (A & B), 0) is treated like (icmp eq (A & B), B)
|
||||||
|
; if B is a single bit constant
|
||||||
|
|
||||||
|
; (icmp eq (A & B), 0) & (icmp eq (A & D), 0) -> (icmp eq (A & (B|D)), 0)
|
||||||
|
define i32 @main3(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 48 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, 0 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main3b(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 16 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp ne i32 %and2, 16 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main3e_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, %argc2 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, %argc3 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, 0 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; (icmp ne (A & B), 0) | (icmp ne (A & D), 0) -> (icmp ne (A & (B|D)), 0)
|
||||||
|
define i32 @main3c(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp ne i32 %and, 0 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 48 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp ne i32 %and2, 0 ; <i1> [#uses=1]
|
||||||
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main3d(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp ne i32 %and, 0 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 16 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, 16 ; <i1> [#uses=1]
|
||||||
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main3f_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, %argc2 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp ne i32 %and, 0 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, %argc3 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp ne i32 %and2, 0 ; <i1> [#uses=1]
|
||||||
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; (icmp eq (A & B), B) & (icmp eq (A & D), D) -> (icmp eq (A & (B|D)), (B|D))
|
||||||
|
define i32 @main4(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and, 7 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 48 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, 48 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main4b(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and, 7 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 16 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp ne i32 %and2, 0 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main4e_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, %argc2 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and, %argc2 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, %argc3 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, %argc3 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; (icmp ne (A & B), B) | (icmp ne (A & D), D) -> (icmp ne (A & (B|D)), (B|D))
|
||||||
|
define i32 @main4c(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp ne i32 %and, 7 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 48 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp ne i32 %and2, 48 ; <i1> [#uses=1]
|
||||||
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main4d(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp ne i32 %and, 7 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 16 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, 0 ; <i1> [#uses=1]
|
||||||
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main4f_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, %argc2 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp ne i32 %and, %argc2 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, %argc3 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp ne i32 %and2, %argc3 ; <i1> [#uses=1]
|
||||||
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; (icmp eq (A & B), A) & (icmp eq (A & D), A) -> (icmp eq (A & (B&D)), A)
|
||||||
|
define i32 @main5_like(i32 %argc, i32 %argc2, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and, 7 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc2, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, 7 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main5e_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, %argc2 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and, %argc ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, %argc3 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, %argc ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; (icmp ne (A & B), A) | (icmp ne (A & D), A) -> (icmp ne (A & (B&D)), A)
|
||||||
|
define i32 @main5c_like(i32 %argc, i32 %argc2, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp ne i32 %and, 7 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc2, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp ne i32 %and2, 7 ; <i1> [#uses=1]
|
||||||
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main5f_like(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, %argc2 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp ne i32 %and, %argc ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, %argc3 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp ne i32 %and2, %argc ; <i1> [#uses=1]
|
||||||
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; (icmp eq (A & B), C) & (icmp eq (A & D), E) -> (icmp eq (A & (B|D)), (C|E))
|
||||||
|
; if B, C, D, E are constant, and it's possible
|
||||||
|
define i32 @main6(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and, 3 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 48 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, 16 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main6b(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and, 3 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 16 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp ne i32 %and2, 0 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; (icmp ne (A & B), C) | (icmp ne (A & D), E) -> (icmp ne (A & (B|D)), (C|E))
|
||||||
|
; if B, C, D, E are constant, and it's possible
|
||||||
|
define i32 @main6c(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp ne i32 %and, 3 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 48 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp ne i32 %and2, 16 ; <i1> [#uses=1]
|
||||||
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
define i32 @main6d(i32 %argc, i8** nocapture %argv) nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and = and i32 %argc, 7 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp ne i32 %and, 3 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, 16 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, 0 ; <i1> [#uses=1]
|
||||||
|
%or.cond = or i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %or.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; test parameter permutations
|
||||||
|
; (B & A) == B & (D & A) == D
|
||||||
|
define i32 @main7a(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and1 = and i32 %argc2, %argc ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and1, %argc2 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc3, %argc ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, %argc3 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; B == (A & B) & D == (A & D)
|
||||||
|
define i32 @main7b(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and1 = and i32 %argc, %argc2 ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %argc2, %and1 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, %argc3 ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %argc3, %and2 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; B == (B & A) & D == (D & A)
|
||||||
|
define i32 @main7c(i32 %argc, i32 %argc2, i32 %argc3, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%and1 = and i32 %argc2, %argc ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %argc2, %and1 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc3, %argc ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %argc3, %and2 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; (A & (B & C)) == (B & C) & (A & (D & E)) == (D & E)
|
||||||
|
define i32 @main7d(i32 %argc, i32 %argc2, i32 %argc3,
|
||||||
|
i32 %argc4, i32 %argc5, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%bc = and i32 %argc2, %argc4 ; <i32> [#uses=1]
|
||||||
|
%de = and i32 %argc3, %argc5 ; <i32> [#uses=1]
|
||||||
|
%and1 = and i32 %argc, %bc ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and1, %bc ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, %de ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, %de ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; ((B & C) & A) == (B & C) & ((D & E) & A) == (D & E)
|
||||||
|
define i32 @main7e(i32 %argc, i32 %argc2, i32 %argc3,
|
||||||
|
i32 %argc4, i32 %argc5, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%bc = and i32 %argc2, %argc4 ; <i32> [#uses=1]
|
||||||
|
%de = and i32 %argc3, %argc5 ; <i32> [#uses=1]
|
||||||
|
%and1 = and i32 %bc, %argc ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %and1, %bc ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %de, %argc ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %and2, %de ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; (B & C) == (A & (B & C)) & (D & E) == (A & (D & E))
|
||||||
|
define i32 @main7f(i32 %argc, i32 %argc2, i32 %argc3,
|
||||||
|
i32 %argc4, i32 %argc5, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%bc = and i32 %argc2, %argc4 ; <i32> [#uses=1]
|
||||||
|
%de = and i32 %argc3, %argc5 ; <i32> [#uses=1]
|
||||||
|
%and1 = and i32 %argc, %bc ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %bc, %and1 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %argc, %de ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %de, %and2 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
||||||
|
; (B & C) == ((B & C) & A) & (D & E) == ((D & E) & A)
|
||||||
|
define i32 @main7g(i32 %argc, i32 %argc2, i32 %argc3,
|
||||||
|
i32 %argc4, i32 %argc5, i8** nocapture %argv)
|
||||||
|
nounwind readnone ssp {
|
||||||
|
entry:
|
||||||
|
%bc = and i32 %argc2, %argc4 ; <i32> [#uses=1]
|
||||||
|
%de = and i32 %argc3, %argc5 ; <i32> [#uses=1]
|
||||||
|
%and1 = and i32 %bc, %argc ; <i32> [#uses=1]
|
||||||
|
%tobool = icmp eq i32 %bc, %and1 ; <i1> [#uses=1]
|
||||||
|
%and2 = and i32 %de, %argc ; <i32> [#uses=1]
|
||||||
|
%tobool3 = icmp eq i32 %de, %and2 ; <i1> [#uses=1]
|
||||||
|
%and.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
|
||||||
|
%storemerge = select i1 %and.cond, i32 0, i32 1 ; <i32> [#uses=1]
|
||||||
|
ret i32 %storemerge
|
||||||
|
}
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue