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Add Encoding T1 entry of emulate_sub_sp_imm to the g_thumb_opcodes table. 

Update emulate_sub_sp_imm to handle Encoding T1.

llvm-svn: 124253
This commit is contained in:
Johnny Chen 2011-01-26 00:08:59 +00:00
parent ad16003517
commit 3fde51b820
2 changed files with 15 additions and 1 deletions
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7
lldb/source/Plugins/Process/Utility/ARMUtils.h
View File

@ -120,6 +120,13 @@ static inline uint32_t ThumbImm12(uint32_t val)
return imm12;
}
// imm32 = ZeroExtend(imm7:'00', 32)
static inline uint32_t ThumbImmScaled(uint32_t val)
{
const uint32_t imm7 = bits(val, 6, 0);
return imm7 * 4;
}
// This function performs the check for the register numbers 13 and 15 that are
// not permitted for many Thumb register specifiers.
static inline bool BadReg(uint32_t n) { return n == 13 || n == 15; }

9
lldb/source/Plugins/Process/Utility/EmulateInstructionARM.cpp
View File

@ -225,6 +225,8 @@ emulate_sub_sp_imm (EmulateInstructionARM *emulator, ARMEncoding encoding)
return false;
uint32_t imm32;
switch (encoding) {
case eEncodingT1:
imm32 = ThumbImmScaled(opcode); // imm32 = ZeroExtend(imm7:'00', 32)
case eEncodingT2:
imm32 = ThumbExpandImm(opcode); // imm32 = ThumbExpandImm(i:imm3:imm8)
break;
@ -326,6 +328,7 @@ emulate_str_rt_sp (EmulateInstructionARM *emulator, ARMEncoding encoding)
static ARMOpcode g_arm_opcodes[] =
{
// push register(s)
{ 0x0fff0000, 0x092d0000, ARMvAll, eEncodingA1, eSize32, emulate_push,
"push <registers> ; <registers> contains more than one register" },
{ 0x0fff0fff, 0x052d0004, ARMvAll, eEncodingA2, eSize32, emulate_push,
@ -342,7 +345,8 @@ static ARMOpcode g_arm_opcodes[] =
static ARMOpcode g_thumb_opcodes[] =
{
{ 0x0000fe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, emulate_push,
// push register(s)
{ 0xfffffe00, 0x0000b400, ARMvAll, eEncodingT1, eSize16, emulate_push,
"push <registers>" },
{ 0xffff0000, 0xe92d0000, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_push,
"push.w <registers> ; <registers> contains more than one register" },
@ -350,6 +354,9 @@ static ARMOpcode g_thumb_opcodes[] =
"push.w <registers> ; <registers> contains one register, <Rt>" },
// adjust the stack pointer
{ 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, emulate_sub_sp_imm,
"sub{s} sp, sp, #<imm>"},
// adjust the stack pointer
{ 0xfbef8f00, 0xf1ad0d00, ARMv6T2|ARMv7, eEncodingT2, eSize32, emulate_sub_sp_imm,
"sub{s}.w sp, sp, #<const>"},
// adjust the stack pointer