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factor the 'sign extended from 8 bit' patterns better so 

that they are not destination type specific.  This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.

llvm-svn: 97629
This commit is contained in:
Chris Lattner 2010-03-03 01:45:01 +00:00
parent e9c46c25a1
commit 3fcbbd8673
3 changed files with 11 additions and 20 deletions
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12
llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -1361,7 +1361,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
Opc = X86::LOCK_DEC16m; Opc = X86::LOCK_DEC16m;
else if (isSub) { else if (isSub) {
if (isCN) { if (isCN) {
if (Predicate_i16immSExt8(Val.getNode())) if (Predicate_immSext8(Val.getNode()))
Opc = X86::LOCK_SUB16mi8; Opc = X86::LOCK_SUB16mi8;
else else
Opc = X86::LOCK_SUB16mi; Opc = X86::LOCK_SUB16mi;
@ -1369,7 +1369,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
Opc = X86::LOCK_SUB16mr; Opc = X86::LOCK_SUB16mr;
} else { } else {
if (isCN) { if (isCN) {
if (Predicate_i16immSExt8(Val.getNode())) if (Predicate_immSext8(Val.getNode()))
Opc = X86::LOCK_ADD16mi8; Opc = X86::LOCK_ADD16mi8;
else else
Opc = X86::LOCK_ADD16mi; Opc = X86::LOCK_ADD16mi;
@ -1384,7 +1384,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
Opc = X86::LOCK_DEC32m; Opc = X86::LOCK_DEC32m;
else if (isSub) { else if (isSub) {
if (isCN) { if (isCN) {
if (Predicate_i32immSExt8(Val.getNode())) if (Predicate_immSext8(Val.getNode()))
Opc = X86::LOCK_SUB32mi8; Opc = X86::LOCK_SUB32mi8;
else else
Opc = X86::LOCK_SUB32mi; Opc = X86::LOCK_SUB32mi;
@ -1392,7 +1392,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
Opc = X86::LOCK_SUB32mr; Opc = X86::LOCK_SUB32mr;
} else { } else {
if (isCN) { if (isCN) {
if (Predicate_i32immSExt8(Val.getNode())) if (Predicate_immSext8(Val.getNode()))
Opc = X86::LOCK_ADD32mi8; Opc = X86::LOCK_ADD32mi8;
else else
Opc = X86::LOCK_ADD32mi; Opc = X86::LOCK_ADD32mi;
@ -1408,7 +1408,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
else if (isSub) { else if (isSub) {
Opc = X86::LOCK_SUB64mr; Opc = X86::LOCK_SUB64mr;
if (isCN) { if (isCN) {
if (Predicate_i64immSExt8(Val.getNode())) if (Predicate_immSext8(Val.getNode()))
Opc = X86::LOCK_SUB64mi8; Opc = X86::LOCK_SUB64mi8;
else if (Predicate_i64immSExt32(Val.getNode())) else if (Predicate_i64immSExt32(Val.getNode()))
Opc = X86::LOCK_SUB64mi32; Opc = X86::LOCK_SUB64mi32;
@ -1416,7 +1416,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) {
} else { } else {
Opc = X86::LOCK_ADD64mr; Opc = X86::LOCK_ADD64mr;
if (isCN) { if (isCN) {
if (Predicate_i64immSExt8(Val.getNode())) if (Predicate_immSext8(Val.getNode()))
Opc = X86::LOCK_ADD64mi8; Opc = X86::LOCK_ADD64mi8;
else if (Predicate_i64immSExt32(Val.getNode())) else if (Predicate_i64immSExt32(Val.getNode()))
Opc = X86::LOCK_ADD64mi32; Opc = X86::LOCK_ADD64mi32;

6
llvm/lib/Target/X86/X86Instr64bit.td
View File

@ -59,11 +59,7 @@ def tls64addr : ComplexPattern<i64, 4, "SelectTLSADDRAddr",
// Pattern fragments. // Pattern fragments.
// //
def i64immSExt8 : PatLeaf<(i64 imm), [{ def i64immSExt8 : PatLeaf<(i64 immSext8)>;
// i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
// sign extended field.
return (int64_t)N->getZExtValue() == (int8_t)N->getZExtValue();
}]>;
def GetLo32XForm : SDNodeXForm<imm, [{ def GetLo32XForm : SDNodeXForm<imm, [{
// Transformation function: get the low 32 bits. // Transformation function: get the low 32 bits.

13
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -343,17 +343,12 @@ def X86_COND_O : PatLeaf<(i8 13)>;
def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
def X86_COND_S : PatLeaf<(i8 15)>; def X86_COND_S : PatLeaf<(i8 15)>;
def i16immSExt8 : PatLeaf<(i16 imm), [{ def immSext8 : PatLeaf<(imm), [{
// i16immSExt8 predicate - True if the 16-bit immediate fits in a 8-bit return N->getSExtValue() == (int8_t)N->getSExtValue();
// sign extended field.
return (int16_t)N->getZExtValue() == (int8_t)N->getZExtValue();
}]>; }]>;
def i32immSExt8 : PatLeaf<(i32 imm), [{ def i16immSExt8 : PatLeaf<(i16 immSext8)>;
// i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit def i32immSExt8 : PatLeaf<(i32 immSext8)>;
// sign extended field.
return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue();
}]>;
// Helper fragments for loads. // Helper fragments for loads.
// It's always safe to treat a anyext i16 load as a i32 load if the i16 is // It's always safe to treat a anyext i16 load as a i32 load if the i16 is