From 3f7985e6ec21c21eb6d6cdd05ab206d0bcf2a770 Mon Sep 17 00:00:00 2001
From: Dmitry Preobrazhensky <dmitry.preobrazhensky@amd.com>
Date: Fri, 21 Aug 2020 14:22:25 +0300
Subject: [PATCH] [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax
 description.

Summary of changes:
- added description of MTBUF instructions and format modifier;
- described limitations of f16 inline constants when used with integer operands;
- updated description of gfx9+ flat global addressing modes;
- v_accvgpr_write_b32 src0 corrections (gfx908);
- minor bugfixing and improvements.
---
 llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst           | 1569 +++++++++--------
 llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst         |    6 +-
 llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst            |  272 +--
 llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst            |  926 +++++-----
 llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst            | 1065 +++++------
 llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst          |    6 +-
 llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst          |    6 +-
 llvm/docs/AMDGPU/gfx1011_src32_2.rst          |   17 +
 llvm/docs/AMDGPU/gfx1011_src32_3.rst          |   17 +
 llvm/docs/AMDGPU/gfx10_addr_mimg.rst          |    2 +-
 llvm/docs/AMDGPU/gfx10_attr.rst               |    1 -
 llvm/docs/AMDGPU/gfx10_bimm16.rst             |    1 -
 llvm/docs/AMDGPU/gfx10_bimm32.rst             |    1 -
 llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst |    2 +-
 llvm/docs/AMDGPU/gfx10_fimm16.rst             |    1 -
 llvm/docs/AMDGPU/gfx10_fimm32.rst             |    1 -
 llvm/docs/AMDGPU/gfx10_hwreg.rst              |    1 -
 llvm/docs/AMDGPU/gfx10_label.rst              |    1 -
 llvm/docs/AMDGPU/gfx10_mad_type_dev.rst       |    1 -
 .../AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst     |    1 -
 llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst      |    1 -
 llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst   |    1 -
 llvm/docs/AMDGPU/gfx10_opt.rst                |    1 -
 llvm/docs/AMDGPU/gfx10_param.rst              |    1 -
 llvm/docs/AMDGPU/gfx10_perm_smem.rst          |    1 -
 llvm/docs/AMDGPU/gfx10_ret.rst                |    1 -
 llvm/docs/AMDGPU/gfx10_sdata64_0.rst          |    2 +-
 llvm/docs/AMDGPU/gfx10_sdst64_0.rst           |    2 +-
 llvm/docs/AMDGPU/gfx10_sdst64_1.rst           |    2 +-
 llvm/docs/AMDGPU/gfx10_simm16.rst             |    1 -
 llvm/docs/AMDGPU/gfx10_src32_1.rst            |    2 +-
 llvm/docs/AMDGPU/gfx10_src32_2.rst            |    2 +-
 llvm/docs/AMDGPU/gfx10_src32_3.rst            |    2 +-
 llvm/docs/AMDGPU/gfx10_src32_4.rst            |   17 +
 llvm/docs/AMDGPU/gfx10_src32_5.rst            |   17 +
 llvm/docs/AMDGPU/gfx10_src32_6.rst            |   17 +
 llvm/docs/AMDGPU/gfx10_ssrc64_0.rst           |    2 +-
 llvm/docs/AMDGPU/gfx10_ssrc64_1.rst           |    2 +-
 llvm/docs/AMDGPU/gfx10_tgt.rst                |    1 -
 llvm/docs/AMDGPU/gfx10_type_dev.rst           |    1 -
 llvm/docs/AMDGPU/gfx10_uimm16.rst             |    1 -
 llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst  |    2 -
 llvm/docs/AMDGPU/gfx10_vcc_32.rst             |    1 -
 llvm/docs/AMDGPU/gfx10_waitcnt.rst            |    1 -
 llvm/docs/AMDGPU/gfx7_attr.rst                |    1 -
 llvm/docs/AMDGPU/gfx7_bimm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx7_bimm32.rst              |    1 -
 llvm/docs/AMDGPU/gfx7_dst_buf_32.rst          |   17 +
 llvm/docs/AMDGPU/gfx7_fimm32.rst              |    1 -
 llvm/docs/AMDGPU/gfx7_hwreg.rst               |    1 -
 llvm/docs/AMDGPU/gfx7_label.rst               |    1 -
 llvm/docs/AMDGPU/gfx7_mod.rst                 |    1 -
 llvm/docs/AMDGPU/gfx7_opt.rst                 |    1 -
 llvm/docs/AMDGPU/gfx7_param.rst               |    1 -
 llvm/docs/AMDGPU/gfx7_ret.rst                 |    1 -
 llvm/docs/AMDGPU/gfx7_simm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx7_tgt.rst                 |    1 -
 llvm/docs/AMDGPU/gfx7_type_dev.rst            |    1 -
 llvm/docs/AMDGPU/gfx7_uimm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx7_waitcnt.rst             |    1 -
 llvm/docs/AMDGPU/gfx8_attr.rst                |    1 -
 llvm/docs/AMDGPU/gfx8_bimm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx8_bimm32.rst              |    1 -
 llvm/docs/AMDGPU/gfx8_dst_buf_32.rst          |   17 +
 llvm/docs/AMDGPU/gfx8_fimm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx8_fimm32.rst              |    1 -
 llvm/docs/AMDGPU/gfx8_hwreg.rst               |    1 -
 llvm/docs/AMDGPU/gfx8_imask.rst               |    1 -
 llvm/docs/AMDGPU/gfx8_label.rst               |    1 -
 .../docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst |    1 -
 llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst       |    1 -
 llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst    |    1 -
 llvm/docs/AMDGPU/gfx8_opt.rst                 |    1 -
 llvm/docs/AMDGPU/gfx8_param.rst               |    1 -
 llvm/docs/AMDGPU/gfx8_perm_smem.rst           |    1 -
 llvm/docs/AMDGPU/gfx8_ret.rst                 |    1 -
 llvm/docs/AMDGPU/gfx8_simm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx8_src32_1.rst             |    2 +-
 llvm/docs/AMDGPU/gfx8_src32_2.rst             |    2 +-
 llvm/docs/AMDGPU/gfx8_src32_3.rst             |    2 +-
 llvm/docs/AMDGPU/gfx8_src32_4.rst             |   17 +
 llvm/docs/AMDGPU/gfx8_src32_5.rst             |   17 +
 llvm/docs/AMDGPU/gfx8_src32_6.rst             |   17 +
 llvm/docs/AMDGPU/gfx8_src32_7.rst             |   17 +
 llvm/docs/AMDGPU/gfx8_tgt.rst                 |    1 -
 llvm/docs/AMDGPU/gfx8_type_dev.rst            |    1 -
 llvm/docs/AMDGPU/gfx8_uimm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx8_waitcnt.rst             |    1 -
 llvm/docs/AMDGPU/gfx900_mad_type_dev.rst      |    1 -
 llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst  |    1 -
 llvm/docs/AMDGPU/gfx900_src32_0.rst           |    2 +-
 llvm/docs/AMDGPU/gfx900_src32_1.rst           |    2 +-
 llvm/docs/AMDGPU/gfx904_mad_type_dev.rst      |    1 -
 llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst  |    1 -
 llvm/docs/AMDGPU/gfx904_src32_0.rst           |    2 +-
 llvm/docs/AMDGPU/gfx904_src32_1.rst           |    2 +-
 llvm/docs/AMDGPU/gfx906_mad_type_dev.rst      |    1 -
 .../AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst    |    1 -
 llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst     |    1 -
 llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst  |    1 -
 llvm/docs/AMDGPU/gfx906_src32_0.rst           |    2 +-
 llvm/docs/AMDGPU/gfx906_src32_1.rst           |    2 +-
 llvm/docs/AMDGPU/gfx906_src32_2.rst           |    2 +-
 llvm/docs/AMDGPU/gfx906_src32_3.rst           |   17 +
 llvm/docs/AMDGPU/gfx906_src32_4.rst           |   17 +
 llvm/docs/AMDGPU/gfx906_type_dev.rst          |    1 -
 llvm/docs/AMDGPU/gfx908_mad_type_dev.rst      |    1 -
 .../AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst    |    1 -
 llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst     |    1 -
 llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst  |    1 -
 llvm/docs/AMDGPU/gfx908_offset_buf.rst        |    2 +-
 llvm/docs/AMDGPU/gfx908_opt.rst               |    1 -
 llvm/docs/AMDGPU/gfx908_ret.rst               |    1 -
 llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst |    2 +-
 llvm/docs/AMDGPU/gfx908_src32_0.rst           |    2 +-
 llvm/docs/AMDGPU/gfx908_src32_1.rst           |    2 +-
 llvm/docs/AMDGPU/gfx908_src32_2.rst           |    2 +-
 llvm/docs/AMDGPU/gfx908_src32_3.rst           |    2 +-
 llvm/docs/AMDGPU/gfx908_src32_4.rst           |   17 +
 llvm/docs/AMDGPU/gfx908_src32_5.rst           |   17 +
 llvm/docs/AMDGPU/gfx908_type_dev.rst          |    1 -
 llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst |    2 -
 llvm/docs/AMDGPU/gfx9_attr.rst                |    1 -
 llvm/docs/AMDGPU/gfx9_bimm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx9_bimm32.rst              |    1 -
 llvm/docs/AMDGPU/gfx9_fimm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx9_fimm32.rst              |    1 -
 llvm/docs/AMDGPU/gfx9_hwreg.rst               |    1 -
 llvm/docs/AMDGPU/gfx9_imask.rst               |    1 -
 llvm/docs/AMDGPU/gfx9_label.rst               |    1 -
 .../docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst |    1 -
 llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst       |    1 -
 llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst    |    1 -
 llvm/docs/AMDGPU/gfx9_opt.rst                 |    1 -
 llvm/docs/AMDGPU/gfx9_param.rst               |    1 -
 llvm/docs/AMDGPU/gfx9_perm_smem.rst           |    1 -
 llvm/docs/AMDGPU/gfx9_ret.rst                 |    1 -
 llvm/docs/AMDGPU/gfx9_simm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx9_src32_1.rst             |    2 +-
 llvm/docs/AMDGPU/gfx9_src32_2.rst             |    2 +-
 llvm/docs/AMDGPU/gfx9_src32_3.rst             |    2 +-
 llvm/docs/AMDGPU/gfx9_src32_4.rst             |   17 +
 llvm/docs/AMDGPU/gfx9_src32_5.rst             |   17 +
 llvm/docs/AMDGPU/gfx9_src32_6.rst             |   17 +
 llvm/docs/AMDGPU/gfx9_src32_7.rst             |   17 +
 llvm/docs/AMDGPU/gfx9_tgt.rst                 |    1 -
 llvm/docs/AMDGPU/gfx9_type_dev.rst            |    1 -
 llvm/docs/AMDGPU/gfx9_uimm16.rst              |    1 -
 llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst   |    2 -
 llvm/docs/AMDGPU/gfx9_waitcnt.rst             |    1 -
 llvm/docs/AMDGPUInstructionNotation.rst       |    2 +-
 llvm/docs/AMDGPUInstructionSyntax.rst         |    6 +-
 llvm/docs/AMDGPUModifierSyntax.rst            |  211 ++-
 llvm/docs/AMDGPUOperandSyntax.rst             |   17 +-
 154 files changed, 2570 insertions(+), 1995 deletions(-)
 create mode 100644 llvm/docs/AMDGPU/gfx1011_src32_2.rst
 create mode 100644 llvm/docs/AMDGPU/gfx1011_src32_3.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_src32_4.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_src32_5.rst
 create mode 100644 llvm/docs/AMDGPU/gfx10_src32_6.rst
 create mode 100644 llvm/docs/AMDGPU/gfx7_dst_buf_32.rst
 create mode 100644 llvm/docs/AMDGPU/gfx8_dst_buf_32.rst
 create mode 100644 llvm/docs/AMDGPU/gfx8_src32_4.rst
 create mode 100644 llvm/docs/AMDGPU/gfx8_src32_5.rst
 create mode 100644 llvm/docs/AMDGPU/gfx8_src32_6.rst
 create mode 100644 llvm/docs/AMDGPU/gfx8_src32_7.rst
 create mode 100644 llvm/docs/AMDGPU/gfx906_src32_3.rst
 create mode 100644 llvm/docs/AMDGPU/gfx906_src32_4.rst
 create mode 100644 llvm/docs/AMDGPU/gfx908_src32_4.rst
 create mode 100644 llvm/docs/AMDGPU/gfx908_src32_5.rst
 create mode 100644 llvm/docs/AMDGPU/gfx9_src32_4.rst
 create mode 100644 llvm/docs/AMDGPU/gfx9_src32_5.rst
 create mode 100644 llvm/docs/AMDGPU/gfx9_src32_6.rst
 create mode 100644 llvm/docs/AMDGPU/gfx9_src32_7.rst

diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
index d0f65ee6d89f..1698bca952d5 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst
@@ -47,6 +47,7 @@ DPP16
     v_bfrev_b32_dpp         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
     v_ceil_f16_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
     v_ceil_f32_dpp          :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_cndmask_b32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`    :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
     v_cos_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
     v_cos_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
     v_cvt_f16_f32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                      :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
@@ -98,6 +99,10 @@ DPP16
     v_min_i32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
     v_min_u32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
     v_mov_b32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_movreld_b32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_movrels_b32_dpp       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_movrelsd_2_b32_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
+    v_movrelsd_b32_dpp      :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                        :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
     v_mul_f16_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
     v_mul_f32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
     v_mul_hi_i32_i24_dpp    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`            :ref:`dpp16_ctrl<amdgpu_synid_dpp16_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` :ref:`fi<amdgpu_synid_fi16>`
@@ -148,6 +153,7 @@ DPP8
     v_bfrev_b32_dpp                :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
     v_ceil_f16_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
     v_ceil_f32_dpp                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_cndmask_b32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`            :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
     v_cos_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
     v_cos_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
     v_cvt_f16_f32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
@@ -199,6 +205,10 @@ DPP8
     v_min_i32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
     v_min_u32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
     v_mov_b32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_movreld_b32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_movrels_b32_dpp              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_movrelsd_2_b32_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
+    v_movrelsd_b32_dpp             :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`                                :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
     v_mul_f16_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
     v_mul_f32_dpp                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
     v_mul_hi_i32_i24_dpp           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`                    :ref:`dpp8_sel<amdgpu_synid_dpp8_sel>` :ref:`fi<amdgpu_synid_fi8>`
@@ -338,6 +348,7 @@ DS
     ds_read2_b64                   :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
     ds_read2st64_b32               :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
     ds_read2st64_b64               :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_addtid_b32             :ref:`vdst<amdgpu_synid10_vdst32_0>`                                           :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_read_b128                   :ref:`vdst<amdgpu_synid10_vdst128_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_read_b32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_read_b64                    :ref:`vdst<amdgpu_synid10_vdst64_0>`,       :ref:`vaddr<amdgpu_synid10_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
@@ -370,6 +381,7 @@ DS
     ds_write2_b64                              :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
     ds_write2st64_b32                          :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata32_0>`,   :ref:`vdata1<amdgpu_synid10_vdata32_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
     ds_write2st64_b64                          :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata0<amdgpu_synid10_vdata64_0>`,   :ref:`vdata1<amdgpu_synid10_vdata64_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_addtid_b32                        :ref:`vdata<amdgpu_synid10_vdata32_0>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_write_b128                              :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_write_b16                               :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_write_b16_d16_hi                        :ref:`vaddr<amdgpu_synid10_addr_ds>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
@@ -463,58 +475,58 @@ FLAT
     flat_store_dwordx4                           :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
     flat_store_short                             :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
     flat_store_short_d16_hi                      :ref:`vaddr<amdgpu_synid10_addr_flat>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`                       :ref:`offset11<amdgpu_synid_flat_offset11>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
-    global_atomic_add              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_add_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_and              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_and_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_cmpswap          :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_cmpswap_x2       :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_dec              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_dec_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_fmax             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_fmax_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_fmin             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_fmin_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_inc              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_inc_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_or               :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_or_x2            :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_smax             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_smax_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_smin             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_smin_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_sub              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_sub_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_swap             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_swap_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_umax             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_umax_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_umin             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_umin_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_xor              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_atomic_xor_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_dword              :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_dwordx2            :ref:`vdst<amdgpu_synid10_vdst64_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_dwordx3            :ref:`vdst<amdgpu_synid10_vdst96_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_dwordx4            :ref:`vdst<amdgpu_synid10_vdst128_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_sbyte              :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_sbyte_d16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_sbyte_d16_hi       :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_short_d16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_short_d16_hi       :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_sshort             :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_ubyte              :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_ubyte_d16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_ubyte_d16_hi       :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_load_ushort             :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_store_byte                            :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_store_byte_d16_hi                     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_store_dword                           :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_store_dwordx2                         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_store_dwordx3                         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata96_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_store_dwordx4                         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_store_short                           :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
-    global_store_short_d16_hi                    :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>`
+    global_atomic_add              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_add_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_and              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_and_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_cmpswap          :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`b32x2<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_cmpswap_x2       :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_dec              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_dec_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_fmax             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_fmax_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_fmin             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`f32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_fmin_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`f64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`f64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_inc              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_inc_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_or               :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_or_x2            :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_smax             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_smax_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_smin             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`s32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_smin_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`s64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`s64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_sub              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_sub_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_swap             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_swap_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_umax             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_umax_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_umin             :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u32<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_umin_x2          :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`::ref:`u64<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_xor              :ref:`vdst<amdgpu_synid10_dst_flat_atomic32>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_atomic_xor_x2           :ref:`vdst<amdgpu_synid10_dst_flat_atomic64>`::ref:`opt<amdgpu_synid10_opt>`,     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    global_load_dword              :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_dwordx2            :ref:`vdst<amdgpu_synid10_vdst64_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_dwordx3            :ref:`vdst<amdgpu_synid10_vdst96_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_dwordx4            :ref:`vdst<amdgpu_synid10_vdst128_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_sbyte              :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_sbyte_d16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_sbyte_d16_hi       :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_short_d16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_short_d16_hi       :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_sshort             :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_ubyte              :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_ubyte_d16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_ubyte_d16_hi       :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_load_ushort             :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_global>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_store_byte                            :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_store_byte_d16_hi                     :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_store_dword                           :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_store_dwordx2                         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata64_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_store_dwordx3                         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata96_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_store_dwordx4                         :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata128_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_store_short                           :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    global_store_short_d16_hi                    :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>`,    :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`saddr<amdgpu_synid10_saddr_flat_global>`          :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
     scratch_load_dword             :ref:`vdst<amdgpu_synid10_vdst32_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
     scratch_load_dwordx2           :ref:`vdst<amdgpu_synid10_vdst64_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
     scratch_load_dwordx3           :ref:`vdst<amdgpu_synid10_vdst96_0>`,         :ref:`vaddr<amdgpu_synid10_vaddr_flat_scratch>`,    :ref:`saddr<amdgpu_synid10_saddr_flat_scratch>`                       :ref:`offset12s<amdgpu_synid_flat_offset12s>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
@@ -543,97 +555,137 @@ MIMG
 
 .. parsed-literal::
 
-    **INSTRUCTION**            **DST**      **SRC0**       **SRC1**     **SRC2**       **MODIFIERS**
-    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    image_atomic_add                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_and                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_cmpswap            :ref:`vdata<amdgpu_synid10_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_dec                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_inc                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_or                 :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_smax               :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_smin               :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_sub                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_swap               :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_umax               :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_umin               :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_atomic_xor                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_gather4          :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b        :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b_cl     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b_cl_o   :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b_o      :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c        :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b      :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b_cl   :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b_o    :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_cl     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_cl_o   :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_l      :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_l_o    :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_lz     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_lz_o   :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_o      :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_cl       :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_cl_o     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_l        :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_l_o      :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_lz       :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_lz_o     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_o        :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_get_lod          :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_get_resinfo      :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_load             :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_load_mip         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_load_mip_pck     :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_load_pck         :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_load_pck_sgn     :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_sample           :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b_cl      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b_cl_o    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b_o       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b_cl    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b_cl_o  :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b_o     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd_cl   :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd_o    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cl      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cl_o    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d_cl    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d_cl_o  :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d_o     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_l       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_l_o     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_lz      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_lz_o    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_o       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd_cl     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd_cl_o   :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd_o      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cl        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cl_o      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d_cl      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d_cl_o    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d_o       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_l         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_l_o       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_lz        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_lz_o      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_o         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid10_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_store                     :ref:`vdata<amdgpu_synid10_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_store_mip                 :ref:`vdata<amdgpu_synid10_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
-    image_store_mip_pck             :ref:`vdata<amdgpu_synid10_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
-    image_store_pck                 :ref:`vdata<amdgpu_synid10_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`,   :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    **INSTRUCTION**                **DST**   **SRC0**       **SRC1**   **SRC2**    **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    image_atomic_add                 :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_and                 :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_cmpswap             :ref:`vdata<amdgpu_synid10_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_dec                 :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_inc                 :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_or                  :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_smax                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_smin                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_sub                 :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_swap                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_umax                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_umin                :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_atomic_xor                 :ref:`vdata<amdgpu_synid10_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid10_ret>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_gather4              :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b            :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl         :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl_o       :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_o          :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c            :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b          :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl       :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl_o     :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_o        :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl         :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl_o       :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l          :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l_o        :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz         :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz_o       :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_o          :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl           :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl_o         :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l            :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l_o          :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz           :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz_o         :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_o            :ref:`vdst<amdgpu_synid10_dst_mimg_gather4>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_get_lod              :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_get_resinfo          :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_load                 :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip             :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip_pck         :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_load_mip_pck_sgn     :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_load_pck             :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_load_pck_sgn         :ref:`vdst<amdgpu_synid10_dst_mimg_regular>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_sample               :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b             :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl          :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl_o        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_o           :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c             :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b           :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl_o      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_o         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd          :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl_g16   :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl_o     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl_o_g16 :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_g16      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_o        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_o_g16    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl          :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl_o        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d           :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl_g16    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl_o      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl_o_g16  :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_g16       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_o         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_o_g16     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l           :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l_o         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz          :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz_o        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_o           :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd            :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl_g16     :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl_o       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl_o_g16   :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_g16        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_o          :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_o_g16      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl            :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl_o          :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d             :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl          :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl_g16      :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl_o        :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl_o_g16    :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_g16         :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_o           :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_o_g16       :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l             :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l_o           :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz            :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz_o          :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_o             :ref:`vdst<amdgpu_synid10_dst_mimg_regular_d16>`, :ref:`vaddr<amdgpu_synid10_addr_mimg>`,     :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`, :ref:`ssamp<amdgpu_synid10_samp_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_store                      :ref:`vdata<amdgpu_synid10_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip                  :ref:`vdata<amdgpu_synid10_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip_pck              :ref:`vdata<amdgpu_synid10_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+    image_store_pck                  :ref:`vdata<amdgpu_synid10_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid10_addr_mimg>`, :ref:`srsrc<amdgpu_synid10_rsrc_mimg>`   :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>`
+
+MTBUF
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                   **DST**   **SRC0**   **SRC1**   **SRC2**    **SRC3**      **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    tbuffer_load_format_d16_x     :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`           :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    tbuffer_load_format_d16_xy    :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`           :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    tbuffer_load_format_d16_xyz   :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`           :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    tbuffer_load_format_d16_xyzw  :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`           :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    tbuffer_load_format_x         :ref:`vdst<amdgpu_synid10_dst_buf_32>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`           :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    tbuffer_load_format_xy        :ref:`vdst<amdgpu_synid10_dst_buf_64>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`           :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    tbuffer_load_format_xyz       :ref:`vdst<amdgpu_synid10_dst_buf_96>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`           :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    tbuffer_load_format_xyzw      :ref:`vdst<amdgpu_synid10_dst_buf_128>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`, :ref:`soffset<amdgpu_synid10_offset_buf>`           :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>`
+    tbuffer_store_format_d16_x          :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>`   :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_xy         :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>`   :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_xyz        :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>`   :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_xyzw       :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>`   :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_x              :ref:`vdata<amdgpu_synid10_vdata32_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>`   :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xy             :ref:`vdata<amdgpu_synid10_vdata64_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>`   :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xyz            :ref:`vdata<amdgpu_synid10_vdata96_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>`   :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xyzw           :ref:`vdata<amdgpu_synid10_vdata128_0>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>`   :ref:`ufmt<amdgpu_synid_ufmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
 
 MUBUF
 -----------------------
@@ -650,6 +702,12 @@ MUBUF
     buffer_atomic_cmpswap_x2           :ref:`vdata<amdgpu_synid10_data_buf_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`b64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
     buffer_atomic_dec                  :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
     buffer_atomic_dec_x2               :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fcmpswap             :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`f32x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fcmpswap_x2          :ref:`vdata<amdgpu_synid10_data_buf_atomic128>`::ref:`dst<amdgpu_synid10_ret>`::ref:`f64x2<amdgpu_synid10_type_dev>`, :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fmax                 :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`f32<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fmax_x2              :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`f64<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fmin                 :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`f32<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fmin_x2              :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`f64<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
     buffer_atomic_inc                  :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
     buffer_atomic_inc_x2               :ref:`vdata<amdgpu_synid10_data_buf_atomic64>`::ref:`dst<amdgpu_synid10_ret>`::ref:`u64<amdgpu_synid10_type_dev>`,   :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
     buffer_atomic_or                   :ref:`vdata<amdgpu_synid10_data_buf_atomic32>`::ref:`dst<amdgpu_synid10_ret>`,       :ref:`vaddr<amdgpu_synid10_addr_buf>`, :ref:`srsrc<amdgpu_synid10_rsrc_buf>`,  :ref:`soffset<amdgpu_synid10_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
@@ -729,9 +787,9 @@ SDWA
     v_cmp_class_f32_sdwa     :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_eq_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_f16_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_f32_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -739,33 +797,33 @@ SDWA
     v_cmp_f_u32_sdwa         :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ge_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_gt_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_le_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lg_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lg_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_f16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_f32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_lt_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ne_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ne_i32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmp_ne_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u16_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ne_u32_sdwa        :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_neq_f16_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_neq_f32_sdwa       :ref:`sdst<amdgpu_synid10_wsdst>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -791,9 +849,9 @@ SDWA
     v_cmpx_class_f32_sdwa               :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`::ref:`b32<amdgpu_synid10_type_dev>`      :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_eq_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_f16_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_f32_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -801,33 +859,33 @@ SDWA
     v_cmpx_f_u32_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ge_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_gt_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_le_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lg_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lg_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_f16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_f32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_lt_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ne_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ne_i32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_cmpx_ne_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u16_sdwa                  :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ne_u32_sdwa                  :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_neq_f16_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_neq_f32_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -849,11 +907,12 @@ SDWA
     v_cmpx_tru_f32_sdwa                 :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_u_f16_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_u_f32_sdwa                   :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cndmask_b32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid10_vcc_32>`  :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cos_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cos_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_f16_f32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_i16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_u16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_i16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_u16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_f32_f16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_f32_i32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_f32_u32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
@@ -864,8 +923,8 @@ SDWA
     v_cvt_flr_i32_f32_sdwa   :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_i16_f16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_i32_f32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_norm_i16_f16_sdwa  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_norm_u16_f16_sdwa  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_norm_i16_f16_sdwa  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_norm_u16_f16_sdwa  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_off_f32_i4_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_rpi_i32_f32_sdwa   :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_u16_f16_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`                       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
@@ -897,6 +956,10 @@ SDWA
     v_min_i32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_min_u32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_mov_b32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_movreld_b32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                       :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_movrels_b32_sdwa       :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_movrelsd_2_b32_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_movrelsd_b32_sdwa      :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`                      :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_mul_f16_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_mul_f32_sdwa           :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_mul_hi_i32_i24_sdwa    :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`src0<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`,     :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1277,86 +1340,86 @@ VOP1
 
     **INSTRUCTION**                    **DST**       **SRC**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_bfrev_b32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_ceil_f16                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_ceil_f32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_bfrev_b32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_ceil_f16                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_ceil_f32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_ceil_f64                     :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
     v_clrexcp
-    v_cos_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cos_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f16_f32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f16_i16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f16_u16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f32_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cos_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cos_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_f16_f32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_f16_i16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_3>`
+    v_cvt_f16_u16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_3>`
+    v_cvt_f32_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_cvt_f32_f64                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
-    v_cvt_f32_i32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f32_u32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f32_ubyte0               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f32_ubyte1               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f32_ubyte2               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f32_ubyte3               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f64_f32                  :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f64_i32                  :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_f64_u32                  :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_flr_i32_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_i16_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_i32_f32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_f32_i32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_f32_u32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_f32_ubyte0               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_f32_ubyte1               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_f32_ubyte2               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_f32_ubyte3               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_f64_f32                  :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_f64_i32                  :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_f64_u32                  :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_flr_i32_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_i16_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_i32_f32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_cvt_i32_f64                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
-    v_cvt_norm_i16_f16             :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_norm_u16_f16             :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_off_f32_i4               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_rpi_i32_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_u16_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_cvt_u32_f32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_cvt_norm_i16_f16             :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_norm_u16_f16             :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_off_f32_i4               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_rpi_i32_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_u16_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_cvt_u32_f32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_cvt_u32_f64                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
-    v_exp_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_exp_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_ffbh_i32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_ffbh_u32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_ffbl_b32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_floor_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_floor_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_exp_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_exp_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_ffbh_i32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_ffbh_u32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_ffbl_b32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_floor_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_floor_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_floor_f64                    :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
-    v_fract_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_fract_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_fract_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_fract_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_fract_f64                    :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
-    v_frexp_exp_i16_f16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_frexp_exp_i32_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_frexp_exp_i16_f16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_frexp_exp_i32_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_frexp_exp_i32_f64            :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
-    v_frexp_mant_f16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_frexp_mant_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_frexp_mant_f16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_frexp_mant_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_frexp_mant_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
-    v_log_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_log_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_mov_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_movreld_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_log_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_log_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_mov_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_movreld_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_movrels_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
     v_movrelsd_2_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
     v_movrelsd_b32                 :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
     v_nop
-    v_not_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_not_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_pipeflush
-    v_rcp_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_rcp_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_rcp_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_rcp_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_rcp_f64                      :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
-    v_rcp_iflag_f32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_rcp_iflag_f32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_readfirstlane_b32            :ref:`sdst<amdgpu_synid10_sdst32_2>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_1>`
-    v_rndne_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_rndne_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_rndne_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_rndne_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_rndne_f64                    :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
-    v_rsq_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_rsq_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_rsq_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_rsq_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_rsq_f64                      :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
-    v_sat_pk_u8_i16                :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_sin_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_sin_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_sqrt_f16                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_sqrt_f32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_sat_pk_u8_i16                :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_sin_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_sin_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_sqrt_f16                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_sqrt_f32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_sqrt_f64                     :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
     v_swap_b32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
     v_swaprel_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
-    v_trunc_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
-    v_trunc_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_1>`
+    v_trunc_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
+    v_trunc_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,     :ref:`src<amdgpu_synid10_src32_2>`
     v_trunc_f64                    :ref:`vdst<amdgpu_synid10_vdst64_0>`,     :ref:`src<amdgpu_synid10_src64_0>`
 
 VOP2
@@ -1366,54 +1429,54 @@ VOP2
 
     **INSTRUCTION**                    **DST0**        **DST1**      **SRC0**        **SRC1**        **SRC2**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_add_co_ci_u32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`
-    v_add_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_add_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_add_nc_u32                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_and_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_ashrrev_i32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cndmask_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`
-    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_fmaak_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`imm32<amdgpu_synid10_fimm16>`
-    v_fmaak_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`imm32<amdgpu_synid10_fimm32>`
-    v_fmac_f16                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_fmac_f32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_fmamk_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`imm32<amdgpu_synid10_fimm16>`,      :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
-    v_fmamk_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`imm32<amdgpu_synid10_fimm32>`,      :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
-    v_ldexp_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>`
-    v_lshlrev_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_lshrrev_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_mac_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_mac_legacy_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_madak_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`imm32<amdgpu_synid10_fimm32>`
-    v_madmk_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`imm32<amdgpu_synid10_fimm32>`,      :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
-    v_max_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_max_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_max_i32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_max_u32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_min_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_min_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_min_i32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_min_u32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_mul_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_mul_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_mul_hi_i32_i24               :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_mul_hi_u32_u24               :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_mul_i32_i24                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_mul_legacy_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_mul_u32_u24                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_or_b32                       :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_pk_fmac_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`f16x2<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`f16x2<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`f16x2<amdgpu_synid10_type_dev>`
-    v_sub_co_ci_u32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`
-    v_sub_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_sub_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_sub_nc_u32                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_subrev_co_ci_u32             :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`
-    v_subrev_f16                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_subrev_f32                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_subrev_nc_u32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_xnor_b32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_xor_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_add_co_ci_u32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`
+    v_add_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_add_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_add_nc_u32                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_and_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_ashrrev_i32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cndmask_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`
+    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_fmaak_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`imm32<amdgpu_synid10_fimm16>`
+    v_fmaak_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`imm32<amdgpu_synid10_fimm32>`
+    v_fmac_f16                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_fmac_f32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_fmamk_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`imm32<amdgpu_synid10_fimm16>`,      :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+    v_fmamk_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`imm32<amdgpu_synid10_fimm32>`,      :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+    v_ldexp_f16                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`i16<amdgpu_synid10_type_dev>`
+    v_lshlrev_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_lshrrev_b32                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mac_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mac_legacy_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_madak_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`imm32<amdgpu_synid10_fimm32>`
+    v_madmk_f32                    :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`imm32<amdgpu_synid10_fimm32>`,      :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`
+    v_max_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_max_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_max_i32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_max_u32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_min_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_min_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_min_i32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_min_u32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_hi_i32_i24               :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_hi_u32_u24               :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_i32_i24                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_legacy_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_mul_u32_u24                  :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_or_b32                       :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_pk_fmac_f16                  :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`f16x2<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`f16x2<amdgpu_synid10_type_dev>`, :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`f16x2<amdgpu_synid10_type_dev>`
+    v_sub_co_ci_u32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`
+    v_sub_f16                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_sub_f32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_sub_nc_u32                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_subrev_co_ci_u32             :ref:`vdst<amdgpu_synid10_vdst32_0>`,       :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_4>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`
+    v_subrev_f16                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_4>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_subrev_f32                   :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_4>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_subrev_nc_u32                :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_4>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_xnor_b32                     :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_xor_b32                      :ref:`vdst<amdgpu_synid10_vdst32_0>`,                 :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
 
 VOP3
 -----------------------
@@ -1422,430 +1485,433 @@ VOP3
 
     **INSTRUCTION**             **DST0**       **DST1**     **SRC0**         **SRC1**        **SRC2**            **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_add3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_add_co_ci_u32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`           :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_co_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_add_co_ci_u32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_co_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_add_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_lshl_u32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_add_nc_i16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_nc_i32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_add_nc_u16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_add_nc_u32_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_alignbit_b32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_alignbyte_b32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_and_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_and_or_b32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_ashrrev_i16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
-    v_ashrrev_i32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
-    v_ashrrev_i64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src64_0>`
-    v_bcnt_u32_b32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_bfe_i32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`
-    v_bfe_u32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_bfi_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_bfm_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_bfrev_b32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
-    v_ceil_f16_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_ceil_f32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_lshl_u32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_add_nc_i16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_nc_i32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_nc_u16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_nc_u32_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_alignbit_b32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_alignbyte_b32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_and_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_and_or_b32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_ashrrev_i16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_5>`::ref:`u16<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_5>`
+    v_ashrrev_i32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_4>`
+    v_ashrrev_i64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src64_0>`
+    v_bcnt_u32_b32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_bfe_i32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`
+    v_bfe_u32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_bfi_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_bfm_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_bfrev_b32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`
+    v_ceil_f16_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_ceil_f64_e64          :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_clrexcp_e64
-    v_cmp_class_f16_e64     :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_cmp_class_f32_e64     :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_cmp_class_f64_e64     :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_cmp_eq_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_eq_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_class_f16_e64     :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_class_f32_e64     :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_class_f64_e64     :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_eq_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_eq_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_eq_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_eq_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_eq_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_eq_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_eq_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_eq_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_eq_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_eq_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_eq_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_eq_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_f_f16_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_f_f32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f16_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_f_f64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_f_i32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_f_i32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_f_i64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_f_u32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_f_u32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_f_u64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_ge_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ge_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_ge_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ge_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_ge_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ge_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_ge_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_ge_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_ge_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_ge_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ge_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_ge_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_ge_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_gt_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_gt_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_gt_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_gt_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_gt_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_gt_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_gt_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_gt_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_gt_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_gt_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_gt_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_gt_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_gt_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_le_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_le_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_le_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_le_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_le_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_le_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_le_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_le_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_le_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_le_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_le_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_le_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_le_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_lg_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lg_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_lg_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_lt_f64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_lt_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_lt_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_lt_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_lt_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_lt_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_lt_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_lt_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_lt_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_lt_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_ne_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_ne_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ne_i16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_ne_i32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_ne_i64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_ne_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmp_ne_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_ne_u16_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmp_ne_u32_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_ne_u64_e64        :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_neq_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_neq_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_neq_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nge_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nge_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nge_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ngt_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ngt_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_ngt_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nle_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nle_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nle_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlg_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlg_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nlg_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlt_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlt_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nlt_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_o_f16_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_o_f32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f16_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_o_f64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_t_i32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_t_i32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_t_i64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_t_u32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmp_t_u32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmp_t_u64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmp_tru_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_tru_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f16_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f32_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_tru_f64_e64       :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_u_f16_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_u_f32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f16_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f32_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_u_f64_e64         :ref:`sdst<amdgpu_synid10_wsdst>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_class_f16_e64                        :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_cmpx_class_f32_e64                        :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_cmpx_class_f64_e64                        :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_cmpx_eq_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_eq_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f16_e64                        :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_class_f32_e64                        :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_class_f64_e64                        :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_eq_f16_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_eq_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_eq_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_eq_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_eq_i16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_eq_i32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_eq_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_eq_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_eq_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_eq_u16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_eq_u32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_eq_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_f_f16_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_f_f32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f16_e64                            :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f32_e64                            :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_f_f64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_f_i32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_f_i32_e64                            :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_f_i64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_f_u32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_f_u32_e64                            :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_f_u64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_ge_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ge_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f16_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_ge_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ge_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_ge_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ge_i16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_ge_i32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_ge_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_ge_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_ge_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ge_u16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_ge_u32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_ge_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_gt_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_gt_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f16_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_gt_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_gt_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_gt_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_gt_i16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_gt_i32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_gt_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_gt_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_gt_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_gt_u16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_gt_u32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_gt_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_le_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_le_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f16_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_le_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_le_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_le_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_le_i16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_le_i32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_le_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_le_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_le_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_le_u16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_le_u32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_le_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_lg_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lg_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f16_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_lg_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_f16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_f32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f16_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_lt_f64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_lt_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_lt_i16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_lt_i32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_lt_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_lt_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_lt_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_lt_u16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_lt_u32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_lt_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_ne_i16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_ne_i32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ne_i16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_ne_i32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_ne_i64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_ne_u16_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cmpx_ne_u32_e64                           :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_ne_u16_e64                           :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_cmpx_ne_u32_e64                           :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_ne_u64_e64                           :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_neq_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_neq_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f16_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f32_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_neq_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nge_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nge_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f16_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f32_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nge_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ngt_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ngt_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f16_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f32_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_ngt_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nle_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nle_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f16_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f32_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nle_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlg_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlg_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f16_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f32_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nlg_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlt_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlt_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f16_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f32_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nlt_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_o_f16_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_o_f32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f16_e64                            :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f32_e64                            :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_o_f64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_t_i32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_t_i32_e64                            :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_t_i64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_t_u32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_cmpx_t_u32_e64                            :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
     v_cmpx_t_u64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`
-    v_cmpx_tru_f16_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_tru_f32_e64                          :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f16_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f32_e64                          :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_tru_f64_e64                          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_u_f16_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_u_f32_e64                            :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f16_e64                            :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f32_e64                            :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_u_f64_e64                            :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cndmask_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`
-    v_cos_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cos_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubeid_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubema_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubesc_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubetc_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_f32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_i16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_f16_u16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_f32_f16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cndmask_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`
+    v_cos_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cos_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_i16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_3>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_u16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_3>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_f16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_cvt_f32_f64_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_i32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_u32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte0_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte1_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte2_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte3_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_f32_e64       :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_i32_e64       :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_u32_e64       :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_flr_i32_f32_e64   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
-    v_cvt_i16_f16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_i32_f32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_i32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64       :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64       :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64       :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_cvt_i16_f16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i32_f32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
     v_cvt_i32_f64_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_norm_i16_f16_e64  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
-    v_cvt_norm_u16_f16_e64  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
-    v_cvt_off_f32_i4_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_i16_i32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cvt_pk_u16_u32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_cvt_pk_u8_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`
-    v_cvt_pknorm_i16_f16    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_cvt_pknorm_i16_f32    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
-    v_cvt_pknorm_u16_f16    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_cvt_pknorm_u16_f32    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
-    v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_rpi_i32_f32_e64   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
-    v_cvt_u16_f16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_u32_f32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_norm_i16_f16_e64  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_norm_u16_f16_e64  :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_off_f32_i4_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_cvt_pk_u16_u32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_cvt_pk_u8_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`
+    v_cvt_pknorm_i16_f16    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_cvt_pknorm_i16_f32    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_cvt_pknorm_u16_f16    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_cvt_pknorm_u16_f32    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_cvt_pkrtz_f16_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_rpi_i32_f32_e64   :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_cvt_u16_f16_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u32_f32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
     v_cvt_u32_f64_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_div_fixup_f16         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_div_fixup_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f16         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fixup_f64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fmas_f32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fmas_f64          :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`,     :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_div_scale_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`,     :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
     v_div_scale_f64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,      :ref:`vcc<amdgpu_synid10_vcc_32>`,     :ref:`src0<amdgpu_synid10_src64_0>`,        :ref:`src1<amdgpu_synid10_src64_0>`,       :ref:`src2<amdgpu_synid10_src64_0>`
-    v_exp_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_exp_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_i32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
-    v_ffbh_u32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
-    v_ffbl_b32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
-    v_floor_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_floor_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_exp_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`
+    v_ffbh_u32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`
+    v_ffbl_b32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`
+    v_floor_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_floor_f64_e64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_fma_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fma_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fmac_f16_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_fmac_f32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_fract_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fmac_f16_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_fmac_f32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fract_f64_e64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
-    v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
     v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`
-    v_frexp_mant_f16_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_frexp_mant_f32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f16_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_frexp_mant_f64_e64    :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_mov_f32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`param<amdgpu_synid10_param>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p1_f32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p1ll_f16       :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`f32<amdgpu_synid10_type_dev>`,           :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`,  :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`                    :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p1lv_f16       :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`f32<amdgpu_synid10_type_dev>`,           :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f16x2<amdgpu_synid10_type_dev>`   :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p2_f16         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`, :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`vsrc2<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid10_type_dev>`     :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_ldexp_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i16<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_ldexp_f32             :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f64             :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lerp_u8               :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`b32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_log_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_log_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lshl_add_u32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_lshl_or_b32           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_2>`
-    v_lshlrev_b16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
-    v_lshlrev_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
-    v_lshlrev_b64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src64_0>`
-    v_lshrrev_b16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
-    v_lshrrev_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`
-    v_lshrrev_b64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src64_0>`
-    v_mac_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mac_legacy_f32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i32_i16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i32_i24           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`::ref:`i32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i64_i32           :ref:`vdst<amdgpu_synid10_vdst64_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src64_0>`::ref:`i64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_legacy_f32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u32_u16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u32_u24           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u64_u32           :ref:`vdst<amdgpu_synid10_vdst64_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src64_0>`::ref:`u64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_max3_f16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_max3_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_i16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_max3_i32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_max3_u16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_max3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_max_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_max_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_interp_p2_f32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid10_attr>`::ref:`b32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`i16<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f32             :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`i32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64             :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`i32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8               :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_log_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_log_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_add_u32          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_lshl_or_b32           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_4>`
+    v_lshlrev_b16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_5>`::ref:`u16<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_5>`
+    v_lshlrev_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_4>`
+    v_lshlrev_b64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src64_0>`
+    v_lshrrev_b16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_5>`::ref:`u16<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_5>`
+    v_lshrrev_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_4>`
+    v_lshrrev_b64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src64_0>`
+    v_mac_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mac_legacy_f32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`,       :ref:`src2<amdgpu_synid10_src32_5>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`,       :ref:`src2<amdgpu_synid10_src32_4>`::ref:`i32<amdgpu_synid10_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i24           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`::ref:`i32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i64_i32           :ref:`vdst<amdgpu_synid10_vdst64_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src64_0>`::ref:`i64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`,       :ref:`src2<amdgpu_synid10_src32_5>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u16           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`,       :ref:`src2<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u24           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u64_u32           :ref:`vdst<amdgpu_synid10_vdst64_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src64_0>`::ref:`u64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`,       :ref:`src2<amdgpu_synid10_src32_5>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_max3_i32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_max3_u16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`,       :ref:`src2<amdgpu_synid10_src32_5>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_max3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_max_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_max_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_i16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_max_i32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_max_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_max_u32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mbcnt_hi_u32_b32      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mbcnt_lo_u32_b32      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_med3_f16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_med3_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_i16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_med3_i32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_med3_u16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_med3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_min3_f16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_min3_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_i16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_min3_i32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_min3_u16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_min3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_min_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_min_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_max_i32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_max_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_max_u32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_mbcnt_hi_u32_b32      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_mbcnt_lo_u32_b32      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_med3_f16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`,       :ref:`src2<amdgpu_synid10_src32_5>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_med3_i32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_med3_u16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`,       :ref:`src2<amdgpu_synid10_src32_5>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_med3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_min3_f16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_f32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`,       :ref:`src2<amdgpu_synid10_src32_5>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_min3_i32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_min3_u16              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`,       :ref:`src2<amdgpu_synid10_src32_5>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_min3_u32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_min_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_min_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_i16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_min_i32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_min_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_min_u32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mov_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
-    v_movreld_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
+    v_min_i16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_min_i32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_min_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_min_u32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_mov_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`
+    v_movreld_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`
     v_movrels_b32_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
     v_movrelsd_2_b32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
     v_movrelsd_b32_e64      :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vsrc<amdgpu_synid10_vsrc32_0>`
-    v_mqsad_pk_u16_u8       :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mqsad_u32_u8          :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b128<amdgpu_synid10_type_dev>`,          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`vsrc2<amdgpu_synid10_vsrc128_0>`::ref:`b128<amdgpu_synid10_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
-    v_msad_u8               :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`b32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mul_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_mul_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mqsad_pk_u16_u8       :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mqsad_u32_u8          :ref:`vdst<amdgpu_synid10_vdst128_0>`::ref:`b128<amdgpu_synid10_type_dev>`,          :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`vsrc2<amdgpu_synid10_vsrc128_0>`::ref:`b128<amdgpu_synid10_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
+    v_msad_u8               :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_mul_f64               :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mul_hi_i32_i24_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mul_hi_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mul_hi_u32_u24_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mul_i32_i24_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mul_legacy_f32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_u16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mul_lo_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mul_u32_u24_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_mullit_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_hi_i32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_mul_hi_i32_i24_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_mul_hi_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_mul_hi_u32_u24_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_mul_i32_i24_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_legacy_f32_e64    :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`
+    v_mul_lo_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_mul_u32_u24_e64       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mullit_f32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_nop_e64
-    v_not_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
-    v_or3_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_or_b32_e64            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_pack_b32_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_perm_b32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
+    v_not_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`
+    v_or3_b32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_or_b32_e64            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_pack_b32_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_perm_b32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
     v_permlane16_b32        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_3>`,      :ref:`ssrc2<amdgpu_synid10_ssrc32_3>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
     v_permlanex16_b32       :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`vdata<amdgpu_synid10_vdata32_0>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_3>`,      :ref:`ssrc2<amdgpu_synid10_ssrc32_3>`           :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
     v_pipeflush_e64
-    v_qsad_pk_u16_u8        :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_2>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_rcp_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rcp_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_qsad_pk_u16_u8        :ref:`vdst<amdgpu_synid10_vdst64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`,    :ref:`src1<amdgpu_synid10_src32_4>`::ref:`b32<amdgpu_synid10_type_dev>`,   :ref:`src2<amdgpu_synid10_src64_0>`::ref:`b64<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rcp_f64_e64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_iflag_f32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_readlane_b32          :ref:`sdst<amdgpu_synid10_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid10_vsrc32_1>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_4>`
-    v_rndne_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rndne_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rndne_f64_e64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rsq_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rsq_f64_e64           :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_hi_u8             :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u8x4<amdgpu_synid10_type_dev>`,   :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u8x4<amdgpu_synid10_type_dev>`,  :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u16x2<amdgpu_synid10_type_dev>`,  :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u8                :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_1>`::ref:`u8x4<amdgpu_synid10_type_dev>`,   :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u8x4<amdgpu_synid10_type_dev>`,  :ref:`src2<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sat_pk_u8_i16_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`
-    v_sin_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_sin_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f16_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_sqrt_f32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8             :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u8x4<amdgpu_synid10_type_dev>`,   :ref:`src1<amdgpu_synid10_src32_4>`::ref:`u8x4<amdgpu_synid10_type_dev>`,  :ref:`src2<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u16               :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`,  :ref:`src1<amdgpu_synid10_src32_4>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src2<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u8                :ref:`vdst<amdgpu_synid10_vdst32_0>`::ref:`u32<amdgpu_synid10_type_dev>`,           :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u8x4<amdgpu_synid10_type_dev>`,   :ref:`src1<amdgpu_synid10_src32_4>`::ref:`u8x4<amdgpu_synid10_type_dev>`,  :ref:`src2<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sat_pk_u8_i16_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`
+    v_sin_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f16_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_sqrt_f64_e64          :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_co_ci_u32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`           :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_co_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_nc_i16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_nc_i32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_sub_nc_u16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_sub_nc_u32_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_co_ci_u32_e64  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`           :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_co_u32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_f16_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_f32_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_nc_u32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_2>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_trig_preop_f64        :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_2>`::ref:`u32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_trunc_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_1>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_co_ci_u32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_co_u32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f16_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_nc_i16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_nc_i32            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_nc_u16            :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_3>`,        :ref:`src1<amdgpu_synid10_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_nc_u32_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_co_ci_u32_e64  :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_4>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`ssrc2<amdgpu_synid10_wssrc>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_co_u32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,      :ref:`sdst<amdgpu_synid10_wsdst>`,    :ref:`src0<amdgpu_synid10_src32_4>`,        :ref:`src1<amdgpu_synid10_src32_4>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f16_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f32_e64        :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_nc_u32_e64     :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_4>`,        :ref:`src1<amdgpu_synid10_src32_4>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_trig_preop_f64        :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src0<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid10_src32_4>`::ref:`u32<amdgpu_synid10_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f16_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f32_e64         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src<amdgpu_synid10_src32_2>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_trunc_f64_e64         :ref:`vdst<amdgpu_synid10_vdst64_0>`,               :ref:`src<amdgpu_synid10_src64_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_writelane_b32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`ssrc0<amdgpu_synid10_ssrc32_5>`,       :ref:`ssrc1<amdgpu_synid10_ssrc32_4>`
-    v_xad_u32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_xnor_b32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
-    v_xor3_b32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`,       :ref:`src2<amdgpu_synid10_src32_2>`
-    v_xor_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_1>`,        :ref:`src1<amdgpu_synid10_src32_2>`
+    v_xad_u32               :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_xnor_b32_e64          :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
+    v_xor3_b32              :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`,       :ref:`src2<amdgpu_synid10_src32_4>`
+    v_xor_b32_e64           :ref:`vdst<amdgpu_synid10_vdst32_0>`,               :ref:`src0<amdgpu_synid10_src32_2>`,        :ref:`src1<amdgpu_synid10_src32_4>`
 
 VOP3P
 -----------------------
@@ -1854,28 +1920,28 @@ VOP3P
 
     **INSTRUCTION**           **DST**      **SRC0**        **SRC1**       **SRC2**        **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_fma_mix_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`,  :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`   :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_fma_mixhi_f16       :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`,  :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`   :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_fma_mixlo_f16       :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`,  :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`   :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_ashrrev_i16      :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_fma_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`,      :ref:`src2<amdgpu_synid10_src32_2>`        :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_lshlrev_b16      :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_lshrrev_b16      :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_mad_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`,      :ref:`src2<amdgpu_synid10_src32_2>`        :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_mad_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`,      :ref:`src2<amdgpu_synid10_src32_2>`        :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_max_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_max_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_max_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_min_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_min_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_min_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_mul_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_mul_lo_u16       :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_sub_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_sub_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_1>`,       :ref:`src1<amdgpu_synid10_src32_2>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_mix_f32         :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_6>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`,  :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`   :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_mixhi_f16       :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_6>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`,  :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`   :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_mixlo_f16       :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_6>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`,  :ref:`src1<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`, :ref:`src2<amdgpu_synid10_src32_0>`::ref:`m<amdgpu_synid10_mod_vop3_abs_neg>`::ref:`fx<amdgpu_synid10_mad_type_dev>`   :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>` :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`src1<amdgpu_synid10_src32_4>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_ashrrev_i16      :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_5>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_fma_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`src1<amdgpu_synid10_src32_4>`,      :ref:`src2<amdgpu_synid10_src32_4>`        :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_lshlrev_b16      :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_5>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_lshrrev_b16      :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_5>`::ref:`u16x2<amdgpu_synid10_type_dev>`, :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mad_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`,      :ref:`src2<amdgpu_synid10_src32_5>`        :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mad_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`,      :ref:`src2<amdgpu_synid10_src32_5>`        :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`src1<amdgpu_synid10_src32_4>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_max_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`src1<amdgpu_synid10_src32_4>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_min_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mul_f16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_2>`,       :ref:`src1<amdgpu_synid10_src32_4>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mul_lo_u16       :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_sub_i16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_sub_u16          :ref:`vdst<amdgpu_synid10_vdst32_0>`,    :ref:`src0<amdgpu_synid10_src32_3>`,       :ref:`src1<amdgpu_synid10_src32_5>`                   :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
 
 VOPC
 -----------------------
@@ -1884,195 +1950,195 @@ VOPC
 
     **INSTRUCTION**                    **DST**       **SRC0**      **SRC1**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_cmp_class_f16                :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_cmp_class_f32                :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_class_f16                :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmp_class_f32                :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
     v_cmp_class_f64                :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_cmp_eq_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_eq_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_eq_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_eq_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_eq_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_eq_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_eq_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_eq_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_eq_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_eq_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_f_f16                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_f_f32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_f_f16                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_f_f32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_f_f64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_f_i32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_f_i32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_f_i64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_f_u32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_f_u32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_f_u64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_ge_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_ge_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_ge_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_ge_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_ge_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_ge_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_ge_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_ge_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ge_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_ge_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_gt_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_gt_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_gt_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_gt_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_gt_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_gt_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_gt_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_gt_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_gt_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_gt_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_le_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_le_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_le_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_le_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_le_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_le_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_le_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_le_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_le_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_le_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_lg_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_lg_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lg_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lg_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_lg_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_lt_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_lt_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_f16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_f32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_lt_f64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_lt_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_lt_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_lt_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_lt_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_lt_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_lt_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_lt_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_ne_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_ne_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ne_i16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ne_i32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_ne_i64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_ne_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_ne_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ne_u16                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ne_u32                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_ne_u64                   :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_neq_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_neq_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_neq_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_neq_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_neq_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_nge_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_nge_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nge_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nge_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_nge_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_ngt_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_ngt_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ngt_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_ngt_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_ngt_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_nle_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_nle_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nle_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nle_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_nle_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_nlg_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_nlg_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nlg_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nlg_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_nlg_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_nlt_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_nlt_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nlt_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_nlt_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_nlt_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_o_f16                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_o_f32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_o_f16                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_o_f32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_o_f64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_t_i32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_t_i32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_t_i64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_t_u32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_t_u32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_t_u64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_tru_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_tru_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_tru_f16                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_tru_f32                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_tru_f64                  :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmp_u_f16                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmp_u_f32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_u_f16                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmp_u_f32                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmp_u_f64                    :ref:`vcc<amdgpu_synid10_vcc_32>`,      :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_class_f16                         :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_cmpx_class_f32                         :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_class_f16                         :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
+    v_cmpx_class_f32                         :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
     v_cmpx_class_f64                         :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`::ref:`b32<amdgpu_synid10_type_dev>`
-    v_cmpx_eq_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_eq_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_f16                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_f32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_eq_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_eq_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_eq_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_i16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_i32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_eq_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_eq_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_eq_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_u16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_eq_u32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_eq_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_f_f16                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_f_f32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_f_f16                             :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_f_f32                             :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_f_f64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_f_i32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_f_i32                             :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_f_i64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_f_u32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_f_u32                             :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_f_u64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_ge_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_ge_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_f16                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_f32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_ge_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_ge_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_ge_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_i16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_i32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_ge_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_ge_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_ge_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_u16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ge_u32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_ge_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_gt_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_gt_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_f16                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_f32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_gt_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_gt_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_gt_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_i16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_i32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_gt_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_gt_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_gt_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_u16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_gt_u32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_gt_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_le_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_le_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_f16                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_f32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_le_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_le_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_le_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_i16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_i32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_le_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_le_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_le_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_u16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_le_u32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_le_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_lg_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_lg_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lg_f16                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lg_f32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_lg_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_lt_f16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_lt_f32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_f16                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_f32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_lt_f64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_lt_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_lt_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_i16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_i32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_lt_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_lt_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_lt_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_u16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_lt_u32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_lt_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_ne_i16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_ne_i32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ne_i16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ne_i32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_ne_i64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_ne_u16                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_ne_u32                            :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ne_u16                            :ref:`src0<amdgpu_synid10_src32_3>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ne_u32                            :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_ne_u64                            :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_neq_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_neq_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_neq_f16                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_neq_f32                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_neq_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_nge_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_nge_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nge_f16                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nge_f32                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_nge_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_ngt_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_ngt_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ngt_f16                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_ngt_f32                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_ngt_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_nle_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_nle_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nle_f16                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nle_f32                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_nle_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_nlg_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_nlg_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nlg_f16                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nlg_f32                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_nlg_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_nlt_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_nlt_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nlt_f16                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_nlt_f32                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_nlt_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_o_f16                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_o_f32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_o_f16                             :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_o_f32                             :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_o_f64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_t_i32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_t_i32                             :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_t_i64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_t_u32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_t_u32                             :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_t_u64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_tru_f16                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_tru_f32                           :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_tru_f16                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_tru_f32                           :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_tru_f64                           :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
-    v_cmpx_u_f16                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
-    v_cmpx_u_f32                             :ref:`src0<amdgpu_synid10_src32_1>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_u_f16                             :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
+    v_cmpx_u_f32                             :ref:`src0<amdgpu_synid10_src32_2>`,     :ref:`vsrc1<amdgpu_synid10_vsrc32_0>`
     v_cmpx_u_f64                             :ref:`src0<amdgpu_synid10_src64_0>`,     :ref:`vsrc1<amdgpu_synid10_vsrc64_0>`
 
 .. |---| unicode:: U+02014 .. em dash
@@ -2146,6 +2212,9 @@ VOPC
     gfx10_src32_1
     gfx10_src32_2
     gfx10_src32_3
+    gfx10_src32_4
+    gfx10_src32_5
+    gfx10_src32_6
     gfx10_src64_0
     gfx10_src_exp
     gfx10_ssrc32_0
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst
index 5e825c693c3e..f2ea91f92163 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst
@@ -71,8 +71,8 @@ VOP3P
     **INSTRUCTION**                    **DST**       **SRC0**        **SRC1**        **SRC2**           **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
     v_dot2_f32_f16                 :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`f16x2<amdgpu_synid1011_type_dev>`, :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`f16x2<amdgpu_synid1011_type_dev>`, :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`f32<amdgpu_synid1011_type_dev>`       :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_i32_i16                 :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`i16x2<amdgpu_synid1011_type_dev>`, :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`i16x2<amdgpu_synid1011_type_dev>`, :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`i32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_u32_u16                 :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`u16x2<amdgpu_synid1011_type_dev>`, :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`u16x2<amdgpu_synid1011_type_dev>`, :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`u32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_i32_i16                 :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_2>`::ref:`i16x2<amdgpu_synid1011_type_dev>`, :ref:`src1<amdgpu_synid1011_src32_3>`::ref:`i16x2<amdgpu_synid1011_type_dev>`, :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`i32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_u32_u16                 :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_2>`::ref:`u16x2<amdgpu_synid1011_type_dev>`, :ref:`src1<amdgpu_synid1011_src32_3>`::ref:`u16x2<amdgpu_synid1011_type_dev>`, :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`u32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_i32_i8                  :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`i8x4<amdgpu_synid1011_type_dev>`,  :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`i8x4<amdgpu_synid1011_type_dev>`,  :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`i32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_u32_u8                  :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`u8x4<amdgpu_synid1011_type_dev>`,  :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`u8x4<amdgpu_synid1011_type_dev>`,  :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`u32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot8_i32_i4                  :ref:`vdst<amdgpu_synid1011_vdst32_0>`,     :ref:`src0<amdgpu_synid1011_src32_0>`::ref:`i4x8<amdgpu_synid1011_type_dev>`,  :ref:`src1<amdgpu_synid1011_src32_1>`::ref:`i4x8<amdgpu_synid1011_type_dev>`,  :ref:`src2<amdgpu_synid1011_src32_1>`::ref:`i32<amdgpu_synid1011_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
@@ -87,6 +87,8 @@ VOP3P
     AMDGPUAsmGFX10
     gfx1011_src32_0
     gfx1011_src32_1
+    gfx1011_src32_2
+    gfx1011_src32_3
     gfx1011_vdst32_0
     gfx1011_vsrc32_0
     gfx1011_type_dev
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
index c1b8512367f8..348285e329b4 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst
@@ -247,7 +247,7 @@ MIMG
 .. parsed-literal::
 
     **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**      **SRC2**           **MODIFIERS**
-    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
     image_atomic_add                         :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_atomic_and                         :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_atomic_cmpswap                     :ref:`vdata<amdgpu_synid7_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
@@ -261,138 +261,160 @@ MIMG
     image_atomic_umax                        :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_atomic_umin                        :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_atomic_xor                         :ref:`vdata<amdgpu_synid7_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid7_ret>`, :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4                  :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_b                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_b_cl             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_b_cl_o           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_b_o              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_b              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_b_cl           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_b_cl_o         :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_b_o            :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_cl             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_cl_o           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_l              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_l_o            :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_lz             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_lz_o           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_c_o              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_cl               :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_cl_o             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_l                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_l_o              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_lz               :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_lz_o             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4_o                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_get_lod                  :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_get_resinfo              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load                     :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_mip                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_mip_pck             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_mip_pck_sgn         :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck_sgn             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample                   :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_b                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_b_cl              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_b_cl_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_b_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_b               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_b_cl            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_b_cl_o          :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_b_o             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_cd              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_cd_cl           :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_cd_cl_o         :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_cd_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_cl              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_cl_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_d               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_d_cl            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_d_cl_o          :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_d_o             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_l               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_l_o             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_lz              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_lz_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_c_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_cd                :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_cd_cl             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_cd_cl_o           :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_cd_o              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_cl                :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_cl_o              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_d                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_d_cl              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_d_cl_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_d_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_l                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_l_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_lz                :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_lz_o              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample_o                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4                  :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b_cl             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b_cl_o           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_b_o              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b_cl           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b_cl_o         :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_b_o            :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_cl             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_cl_o           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_l              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_l_o            :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_lz             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_lz_o           :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_c_o              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_cl               :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_cl_o             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_l                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_l_o              :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_lz               :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_lz_o             :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4_o                :ref:`vdst<amdgpu_synid7_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_lod                  :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_resinfo              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load                     :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip_pck             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip_pck_sgn         :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck_sgn             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample                   :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_b                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_b_cl              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_b_cl_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_b_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_b               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_b_cl            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_b_cl_o          :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_b_o             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cd              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cd_cl           :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cd_cl_o         :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cd_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cl              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_cl_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_d               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_d_cl            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_d_cl_o          :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_d_o             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_l               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_l_o             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_lz              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_lz_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_c_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cd                :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cd_cl             :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cd_cl_o           :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cd_o              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cl                :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_cl_o              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_d                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_d_cl              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_d_cl_o            :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_d_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_l                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_l_o               :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_lz                :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_lz_o              :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample_o                 :ref:`vdst<amdgpu_synid7_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,     :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid7_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_store                              :ref:`vdata<amdgpu_synid7_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_store_mip                          :ref:`vdata<amdgpu_synid7_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_store_mip_pck                      :ref:`vdata<amdgpu_synid7_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_store_pck                          :ref:`vdata<amdgpu_synid7_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid7_addr_mimg>`,    :ref:`srsrc<amdgpu_synid7_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
 
+MTBUF
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**               **DST**   **SRC0**   **SRC1**   **SRC2**    **SRC3**      **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    tbuffer_load_format_x     :ref:`vdst<amdgpu_synid7_dst_buf_32>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_xy    :ref:`vdst<amdgpu_synid7_dst_buf_64>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_xyz   :ref:`vdst<amdgpu_synid7_dst_buf_96>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_xyzw  :ref:`vdst<amdgpu_synid7_dst_buf_128>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_x          :ref:`vdata<amdgpu_synid7_vdata32_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xy         :ref:`vdata<amdgpu_synid7_vdata64_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xyz        :ref:`vdata<amdgpu_synid7_vdata96_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xyzw       :ref:`vdata<amdgpu_synid7_vdata128_0>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
 MUBUF
 -----------------------
 
 .. parsed-literal::
 
-    **INSTRUCTION**              **DST**   **SRC0**             **SRC1**   **SRC2**    **SRC3**    **MODIFIERS**
-    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    buffer_atomic_add              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_add_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_and              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_and_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_cmpswap          :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_cmpswap_x2       :ref:`vdata<amdgpu_synid7_data_buf_atomic128>`::ref:`dst<amdgpu_synid7_ret>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_dec              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_dec_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_inc              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_inc_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_or               :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_or_x2            :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smax             :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smax_x2          :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smin             :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_smin_x2          :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_sub              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_sub_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_swap             :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_swap_x2          :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umax             :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umax_x2          :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umin             :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_umin_x2          :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_xor              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_atomic_xor_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dword        :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_dwordx2      :ref:`vdst<amdgpu_synid7_dst_buf_64>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dwordx3      :ref:`vdst<amdgpu_synid7_dst_buf_96>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_dwordx4      :ref:`vdst<amdgpu_synid7_dst_buf_128>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_x     :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_format_xy    :ref:`vdst<amdgpu_synid7_dst_buf_64>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_xyz   :ref:`vdst<amdgpu_synid7_dst_buf_96>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_format_xyzw  :ref:`vdst<amdgpu_synid7_dst_buf_128>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_load_sbyte        :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_sshort       :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_ubyte        :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_load_ushort       :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
-    buffer_store_byte              :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dword             :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx2           :ref:`vdata<amdgpu_synid7_vdata64_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx3           :ref:`vdata<amdgpu_synid7_vdata96_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_dwordx4           :ref:`vdata<amdgpu_synid7_vdata128_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_x          :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xy         :ref:`vdata<amdgpu_synid7_vdata64_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xyz        :ref:`vdata<amdgpu_synid7_vdata96_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_format_xyzw       :ref:`vdata<amdgpu_synid7_vdata128_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
-    buffer_store_short             :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    **INSTRUCTION**               **DST**   **SRC0**             **SRC1**   **SRC2**    **SRC3**    **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    buffer_atomic_add               :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_add_x2            :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and               :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_and_x2            :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`b32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_cmpswap_x2        :ref:`vdata<amdgpu_synid7_data_buf_atomic128>`::ref:`dst<amdgpu_synid7_ret>`::ref:`b64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec               :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_dec_x2            :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fcmpswap          :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`f32x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fcmpswap_x2       :ref:`vdata<amdgpu_synid7_data_buf_atomic128>`::ref:`dst<amdgpu_synid7_ret>`::ref:`f64x2<amdgpu_synid7_type_dev>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fmax              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`f32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fmax_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`f64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fmin              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`f32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_fmin_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`f64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc               :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_inc_x2            :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or                :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_or_x2             :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smax_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_smin_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`s64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub               :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_sub_x2            :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_swap_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umax_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin              :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u32<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_umin_x2           :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`::ref:`u64<amdgpu_synid7_type_dev>`,   :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor               :ref:`vdata<amdgpu_synid7_data_buf_atomic32>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_atomic_xor_x2            :ref:`vdata<amdgpu_synid7_data_buf_atomic64>`::ref:`dst<amdgpu_synid7_ret>`,       :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dword         :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_dwordx2       :ref:`vdst<amdgpu_synid7_dst_buf_64>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx3       :ref:`vdst<amdgpu_synid7_dst_buf_96>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_dwordx4       :ref:`vdst<amdgpu_synid7_dst_buf_128>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_x      :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_format_xy     :ref:`vdst<amdgpu_synid7_dst_buf_64>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyz    :ref:`vdst<amdgpu_synid7_dst_buf_96>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_format_xyzw   :ref:`vdst<amdgpu_synid7_dst_buf_128>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_load_sbyte         :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_sshort        :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ubyte         :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_load_ushort        :ref:`vdst<amdgpu_synid7_dst_buf_lds>`, :ref:`vaddr<amdgpu_synid7_addr_buf>`,           :ref:`srsrc<amdgpu_synid7_rsrc_buf>`, :ref:`soffset<amdgpu_synid7_offset_buf>`         :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>`
+    buffer_store_byte               :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dword              :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx2            :ref:`vdata<amdgpu_synid7_vdata64_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx3            :ref:`vdata<amdgpu_synid7_vdata96_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_dwordx4            :ref:`vdata<amdgpu_synid7_vdata128_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_x           :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xy          :ref:`vdata<amdgpu_synid7_vdata64_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyz         :ref:`vdata<amdgpu_synid7_vdata96_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_format_xyzw        :ref:`vdata<amdgpu_synid7_vdata128_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    buffer_store_short              :ref:`vdata<amdgpu_synid7_vdata32_0>`,           :ref:`vaddr<amdgpu_synid7_addr_buf>`, :ref:`srsrc<amdgpu_synid7_rsrc_buf>`,  :ref:`soffset<amdgpu_synid7_offset_buf>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`addr64<amdgpu_synid_addr64>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
     buffer_wbinvl1
     buffer_wbinvl1_vol
 
@@ -451,7 +473,6 @@ SOP1
     s_getpc_b64                    :ref:`sdst<amdgpu_synid7_sdst64_1>`
     s_mov_b32                      :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
     s_mov_b64                      :ref:`sdst<amdgpu_synid7_sdst64_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
-    s_mov_fed_b32                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
     s_movreld_b32                  :ref:`sdst<amdgpu_synid7_sdst32_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_0>`
     s_movreld_b64                  :ref:`sdst<amdgpu_synid7_sdst64_0>`,     :ref:`ssrc<amdgpu_synid7_ssrc64_0>`
     s_movrels_b32                  :ref:`sdst<amdgpu_synid7_sdst32_1>`,     :ref:`ssrc<amdgpu_synid7_ssrc32_2>`
@@ -671,7 +692,6 @@ VOP1
     v_log_f32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
     v_log_legacy_f32               :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
     v_mov_b32                      :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
-    v_mov_fed_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
     v_movreld_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`src<amdgpu_synid7_src32_0>`
     v_movrels_b32                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
     v_movrelsd_b32                 :ref:`vdst<amdgpu_synid7_vdst32_0>`,     :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
@@ -1072,7 +1092,6 @@ VOP3
     v_min_legacy_f32_e64           :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`::ref:`m<amdgpu_synid7_mod>`,     :ref:`src1<amdgpu_synid7_src32_4>`::ref:`m<amdgpu_synid7_mod>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_min_u32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src0<amdgpu_synid7_src32_3>`,       :ref:`src1<amdgpu_synid7_src32_4>`
     v_mov_b32_e64                  :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
-    v_mov_fed_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
     v_movreld_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`src<amdgpu_synid7_src32_3>`
     v_movrels_b32_e64              :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
     v_movrelsd_b32_e64             :ref:`vdst<amdgpu_synid7_vdst32_0>`,                :ref:`vsrc<amdgpu_synid7_vsrc32_0>`
@@ -1361,6 +1380,7 @@ VOPC
     gfx7_data_mimg_atomic_reg
     gfx7_data_mimg_store
     gfx7_dst_buf_128
+    gfx7_dst_buf_32
     gfx7_dst_buf_64
     gfx7_dst_buf_96
     gfx7_dst_buf_lds
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
index b41d5e6eaf94..f08457e3db23 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst
@@ -245,97 +245,121 @@ MIMG
 
 .. parsed-literal::
 
-    **INSTRUCTION**                    **DST**       **SRC0**       **SRC1**      **SRC2**           **MODIFIERS**
-    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    image_atomic_add                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_and                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_cmpswap                     :ref:`vdata<amdgpu_synid8_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_dec                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_inc                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_or                          :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_smax                        :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_smin                        :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_sub                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_swap                        :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_umax                        :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_umin                        :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_atomic_xor                         :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_gather4                  :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b                :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b_cl             :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b_cl_o           :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_b_o              :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c                :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b              :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b_cl           :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b_cl_o         :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_b_o            :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_cl             :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_cl_o           :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_l              :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_l_o            :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_lz             :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_lz_o           :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_c_o              :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_cl               :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_cl_o             :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_l                :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_l_o              :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_lz               :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_lz_o             :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_gather4_o                :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_get_lod                  :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_get_resinfo              :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load                     :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_load_mip                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_load_mip_pck             :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_mip_pck_sgn         :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck_sgn             :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`                    :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample                   :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b_cl              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b_cl_o            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b_o               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b_cl            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b_cl_o          :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b_o             :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd_cl           :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd_cl_o         :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd_o            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cl              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cl_o            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d_cl            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d_cl_o          :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d_o             :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_l               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_l_o             :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_lz              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_lz_o            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_o               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd                :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd_cl             :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd_cl_o           :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd_o              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cl                :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cl_o              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d_cl              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d_cl_o            :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d_o               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_l                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_l_o               :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_lz                :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_lz_o              :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_o                 :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,    :ref:`ssamp<amdgpu_synid8_samp_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_store                              :ref:`vdata<amdgpu_synid8_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_store_mip                          :ref:`vdata<amdgpu_synid8_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_store_mip_pck                      :ref:`vdata<amdgpu_synid8_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_store_pck                          :ref:`vdata<amdgpu_synid8_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,    :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`          :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    **INSTRUCTION**            **DST**      **SRC0**       **SRC1**     **SRC2**       **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    image_atomic_add                :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_and                :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_cmpswap            :ref:`vdata<amdgpu_synid8_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_dec                :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_inc                :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_or                 :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smax               :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_smin               :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_sub                :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_swap               :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umax               :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_umin               :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_atomic_xor                :ref:`vdata<amdgpu_synid8_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid8_ret>`, :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_gather4          :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b        :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl     :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_cl_o   :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_b_o      :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c        :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b      :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl   :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_cl_o :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_b_o    :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl     :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_cl_o   :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l      :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_l_o    :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz     :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_lz_o   :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_c_o      :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl       :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_cl_o     :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l        :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_l_o      :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz       :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_lz_o     :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_gather4_o        :ref:`vdst<amdgpu_synid8_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_get_lod          :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_resinfo      :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load             :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip         :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip_pck     :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck         :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck_sgn     :ref:`vdst<amdgpu_synid8_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample           :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b         :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl      :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl_o    :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_o       :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c         :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b       :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl    :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl_o  :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_o     :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd      :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl   :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_o    :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl      :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl_o    :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d       :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl    :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl_o  :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_o     :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l       :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l_o     :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz      :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz_o    :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_o       :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd        :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl     :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl_o   :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_o      :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl        :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl_o      :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d         :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl      :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl_o    :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_o       :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l         :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l_o       :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz        :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz_o      :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_o         :ref:`vdst<amdgpu_synid8_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid8_addr_mimg>`,     :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid8_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store                     :ref:`vdata<amdgpu_synid8_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip                 :ref:`vdata<amdgpu_synid8_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_store_mip_pck             :ref:`vdata<amdgpu_synid8_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_store_pck                 :ref:`vdata<amdgpu_synid8_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid8_addr_mimg>`,   :ref:`srsrc<amdgpu_synid8_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+
+MTBUF
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                   **DST**   **SRC0**   **SRC1**   **SRC2**    **SRC3**      **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    tbuffer_load_format_d16_x     :ref:`vdst<amdgpu_synid8_dst_buf_d16_32>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`, :ref:`soffset<amdgpu_synid8_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_d16_xy    :ref:`vdst<amdgpu_synid8_dst_buf_d16_64>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`, :ref:`soffset<amdgpu_synid8_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_d16_xyz   :ref:`vdst<amdgpu_synid8_dst_buf_d16_96>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`, :ref:`soffset<amdgpu_synid8_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_d16_xyzw  :ref:`vdst<amdgpu_synid8_dst_buf_d16_128>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`, :ref:`soffset<amdgpu_synid8_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_x         :ref:`vdst<amdgpu_synid8_dst_buf_32>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`, :ref:`soffset<amdgpu_synid8_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_xy        :ref:`vdst<amdgpu_synid8_dst_buf_64>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`, :ref:`soffset<amdgpu_synid8_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_xyz       :ref:`vdst<amdgpu_synid8_dst_buf_96>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`, :ref:`soffset<amdgpu_synid8_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_xyzw      :ref:`vdst<amdgpu_synid8_dst_buf_128>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`, :ref:`soffset<amdgpu_synid8_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_x          :ref:`vdata<amdgpu_synid8_data_buf_d16_32>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,  :ref:`soffset<amdgpu_synid8_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_xy         :ref:`vdata<amdgpu_synid8_data_buf_d16_64>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,  :ref:`soffset<amdgpu_synid8_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_xyz        :ref:`vdata<amdgpu_synid8_data_buf_d16_96>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,  :ref:`soffset<amdgpu_synid8_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_xyzw       :ref:`vdata<amdgpu_synid8_data_buf_d16_128>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,  :ref:`soffset<amdgpu_synid8_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_x              :ref:`vdata<amdgpu_synid8_vdata32_0>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,  :ref:`soffset<amdgpu_synid8_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xy             :ref:`vdata<amdgpu_synid8_vdata64_0>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,  :ref:`soffset<amdgpu_synid8_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xyz            :ref:`vdata<amdgpu_synid8_vdata96_0>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,  :ref:`soffset<amdgpu_synid8_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xyzw           :ref:`vdata<amdgpu_synid8_vdata128_0>`, :ref:`vaddr<amdgpu_synid8_addr_buf>`, :ref:`srsrc<amdgpu_synid8_rsrc_buf>`,  :ref:`soffset<amdgpu_synid8_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
 
 MUBUF
 -----------------------
@@ -470,7 +494,6 @@ SOP1
     s_getpc_b64                    :ref:`sdst<amdgpu_synid8_sdst64_1>`
     s_mov_b32                      :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
     s_mov_b64                      :ref:`sdst<amdgpu_synid8_sdst64_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
-    s_mov_fed_b32                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
     s_movreld_b32                  :ref:`sdst<amdgpu_synid8_sdst32_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_0>`
     s_movreld_b64                  :ref:`sdst<amdgpu_synid8_sdst64_0>`,     :ref:`ssrc<amdgpu_synid8_ssrc64_0>`
     s_movrels_b32                  :ref:`sdst<amdgpu_synid8_sdst32_1>`,     :ref:`ssrc<amdgpu_synid8_ssrc32_1>`
@@ -678,10 +701,10 @@ VOP1
     v_cvt_f16_f32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
     v_cvt_f16_f32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_cvt_f16_f32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_i16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f16_i16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_1>`
     v_cvt_f16_i16_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_cvt_f16_i16_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_u16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
+    v_cvt_f16_u16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_1>`
     v_cvt_f16_u16_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_cvt_f16_u16_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_f32_f16                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
@@ -790,9 +813,6 @@ VOP1
     v_mov_b32                      :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
     v_mov_b32_dpp                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_mov_b32_sdwa                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_mov_fed_b32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
-    v_mov_fed_b32_dpp              :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mov_fed_b32_sdwa             :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`         :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_movreld_b32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`src<amdgpu_synid8_src32_0>`
     v_movrels_b32                  :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
     v_movrelsd_b32                 :ref:`vdst<amdgpu_synid8_vdst32_0>`,     :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
@@ -859,7 +879,7 @@ VOP2
     v_add_f32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_add_f32_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_add_f32_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_add_u16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_add_u16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_add_u16_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_add_u16_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_add_u32             :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -871,10 +891,10 @@ VOP2
     v_and_b32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_and_b32_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_and_b32_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_ashrrev_i16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_ashrrev_i16_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_ashrrev_i16_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_ashrrev_i32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_ashrrev_i32_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_ashrrev_i32_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cndmask_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
@@ -883,16 +903,16 @@ VOP2
     v_ldexp_f16           :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`i16<amdgpu_synid8_type_dev>`
     v_ldexp_f16_dpp       :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`i16<amdgpu_synid8_type_dev>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_ldexp_f16_sdwa      :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`i16<amdgpu_synid8_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshlrev_b16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_lshlrev_b16_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_lshlrev_b16_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshlrev_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_lshlrev_b32_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_lshlrev_b32_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshrrev_b16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_lshrrev_b16_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u16<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_lshrrev_b16_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u16<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_lshrrev_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_lshrrev_b32_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_lshrrev_b32_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`::ref:`u32<amdgpu_synid8_type_dev>`, :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_mac_f16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -911,13 +931,13 @@ VOP2
     v_max_f32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_max_f32_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_max_f32_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_i16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_max_i16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_max_i16_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_max_i16_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_max_i32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_max_i32_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_max_i32_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_u16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_max_u16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_max_u16_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_max_u16_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_max_u32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -929,13 +949,13 @@ VOP2
     v_min_f32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_min_f32_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_min_f32_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_i16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_min_i16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_min_i16_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_min_i16_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_min_i32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_min_i32_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_min_i32_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_u16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_min_u16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_min_u16_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_min_u16_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_min_u32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -959,7 +979,7 @@ VOP2
     v_mul_legacy_f32      :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_mul_legacy_f32_dpp  :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_mul_legacy_f32_sdwa :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_lo_u16          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_mul_lo_u16          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_mul_lo_u16_dpp      :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_mul_lo_u16_sdwa     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_mul_u32_u24         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -974,7 +994,7 @@ VOP2
     v_sub_f32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_sub_f32_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_sub_f32_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_u16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_sub_u16             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_sub_u16_dpp         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_sub_u16_sdwa        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_sub_u32             :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -983,19 +1003,19 @@ VOP2
     v_subb_u32            :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
     v_subb_u32_dpp        :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subb_u32_sdwa       :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid8_vcc_64>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subbrev_u32         :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
+    v_subbrev_u32         :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_3>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`
     v_subbrev_u32_dpp     :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subbrev_u32_sdwa    :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid8_vcc_64>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f16          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_f16          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_3>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_subrev_f16_dpp      :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subrev_f16_sdwa     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_f32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_3>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_subrev_f32_dpp      :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subrev_f32_sdwa     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u16          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_u16          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_subrev_u16_dpp      :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subrev_u16_sdwa     :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u32          :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_1>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_subrev_u32          :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`src0<amdgpu_synid8_src32_3>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_subrev_u32_dpp      :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`,       :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subrev_u32_sdwa     :ref:`vdst<amdgpu_synid8_vdst32_0>`, :ref:`vcc<amdgpu_synid8_vcc_64>`, :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_xor_b32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`src0<amdgpu_synid8_src32_0>`,        :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
@@ -1009,290 +1029,290 @@ VOP3
 
     **INSTRUCTION**             **DST0**       **DST1**     **SRC0**         **SRC1**        **SRC2**            **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_add_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_add_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_add_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_addc_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
-    v_alignbit_b32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_alignbyte_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_and_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_ashrrev_i16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
-    v_ashrrev_i32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
-    v_ashrrev_i64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
-    v_bcnt_u32_b32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_bfe_i32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`
-    v_bfe_u32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_bfi_b32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_bfm_b32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_bfrev_b32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
-    v_ceil_f16_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_ceil_f32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_addc_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_alignbit_b32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_alignbyte_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_and_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_ashrrev_i16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_7>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_7>`
+    v_ashrrev_i32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_5>`
+    v_ashrrev_i64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
+    v_bcnt_u32_b32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_bfe_i32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`
+    v_bfe_u32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_bfi_b32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_bfm_b32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_bfrev_b32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`
+    v_ceil_f16_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_ceil_f64_e64          :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_clrexcp_e64
-    v_cmp_class_f16_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmp_class_f32_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmp_class_f64_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmp_eq_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_eq_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_class_f16_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_class_f32_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_class_f64_e64     :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmp_eq_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_eq_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_eq_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_eq_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_eq_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_eq_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_eq_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_eq_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_eq_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_eq_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_eq_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_eq_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_f_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_f_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_f_f64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_f_i16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_f_i32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_f_i16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_f_i32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_f_i64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_f_u16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_f_u32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_f_u16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_f_u32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_f_u64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_ge_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ge_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_ge_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ge_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_ge_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_ge_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_ge_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_ge_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_ge_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_ge_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_ge_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_ge_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_ge_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_gt_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_gt_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_gt_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_gt_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_gt_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_gt_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_gt_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_gt_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_gt_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_gt_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_gt_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_gt_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_gt_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_le_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_le_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_le_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_le_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_le_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_le_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_le_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_le_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_le_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_le_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_le_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_le_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_le_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_lg_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lg_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_lg_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_lt_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_lt_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_lt_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_lt_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_lt_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_lt_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_lt_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_lt_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_lt_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_lt_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_ne_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_ne_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_ne_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_ne_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_ne_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_ne_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_ne_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_ne_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_ne_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_ne_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_neq_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_neq_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_neq_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nge_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nge_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nge_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ngt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ngt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_ngt_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nle_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nle_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nle_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlg_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlg_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nlg_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nlt_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_o_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_o_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_o_f64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_t_i16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_t_i32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_t_i16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_t_i32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_t_i64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_t_u16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmp_t_u32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmp_t_u16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmp_t_u32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmp_t_u64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmp_tru_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_tru_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_tru_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_u_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_u_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f16_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f32_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_u_f64_e64         :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_class_f16_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmpx_class_f32_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmpx_class_f64_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_cmpx_eq_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_eq_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f16_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_class_f32_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_class_f64_e64    :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_cmpx_eq_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_eq_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_eq_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_eq_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_eq_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_eq_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_eq_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_eq_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_eq_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_eq_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_eq_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_eq_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_f_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_f_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_f_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_f_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_f_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_f_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_f_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_f_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_f_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_f_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_f_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_f_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_f_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_ge_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ge_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_ge_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ge_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_ge_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_ge_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_ge_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_ge_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_ge_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_ge_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_ge_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_ge_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_ge_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_gt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_gt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_gt_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_gt_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_gt_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_gt_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_gt_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_gt_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_gt_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_gt_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_gt_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_gt_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_gt_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_le_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_le_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_le_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_le_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_le_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_le_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_le_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_le_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_le_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_le_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_le_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_le_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_le_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_lg_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lg_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_lg_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_lt_f64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_lt_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_lt_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_lt_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_lt_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_lt_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_lt_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_lt_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_lt_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_lt_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_ne_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_ne_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_ne_i16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_ne_i32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_ne_i64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_ne_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_ne_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_ne_u16_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_ne_u32_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_ne_u64_e64       :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_neq_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_neq_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_neq_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nge_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nge_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nge_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ngt_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ngt_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_ngt_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nle_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nle_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nle_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlg_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlg_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nlg_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlt_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlt_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nlt_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_o_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_o_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_o_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_t_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_t_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_t_i16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_t_i32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_t_i64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_t_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cmpx_t_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_cmpx_t_u16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_cmpx_t_u32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
     v_cmpx_t_u64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`
-    v_cmpx_tru_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_tru_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f16_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f32_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_tru_f64_e64      :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_u_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_u_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f16_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f32_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_u_f64_e64        :ref:`sdst<amdgpu_synid8_sdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cndmask_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
-    v_cos_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cos_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubeid_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubema_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubesc_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubetc_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_i16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_f16_u16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_f32_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cndmask_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`
+    v_cos_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cos_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_i16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_6>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_u16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_6>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_cvt_f32_f64_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_i32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_u32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte0_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte1_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte2_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte3_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_f32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_i32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_u32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_flr_i32_f32_e64   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_i16_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_i32_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_f32_i32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64       :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_i16_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_i32_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
     v_cvt_i32_f64_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_off_f32_i4_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_i16_i32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cvt_pk_u16_u32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_cvt_pk_u8_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`
-    v_cvt_pkaccum_u8_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`
-    v_cvt_pknorm_i16_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_pknorm_u16_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_pkrtz_f16_f32     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_rpi_i32_f32_e64   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_u16_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_cvt_u32_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_off_f32_i4_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_cvt_pk_u16_u32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_cvt_pk_u8_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`
+    v_cvt_pkaccum_u8_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`
+    v_cvt_pknorm_i16_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_pknorm_u16_f32    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_pkrtz_f16_f32     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_rpi_i32_f32_e64   :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_u16_f16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_cvt_u32_f32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
     v_cvt_u32_f64_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_div_fixup_f16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_div_fixup_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fixup_f64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fmas_f32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fmas_f32          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fmas_f64          :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`,     :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
+    v_div_scale_f32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`,     :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
     v_div_scale_f64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`vcc<amdgpu_synid8_vcc_64>`,     :ref:`src0<amdgpu_synid8_src64_1>`,        :ref:`src1<amdgpu_synid8_src64_1>`,       :ref:`src2<amdgpu_synid8_src64_1>`
-    v_exp_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_exp_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_exp_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_i32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
-    v_ffbh_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
-    v_ffbl_b32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
-    v_floor_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_floor_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_exp_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`
+    v_ffbh_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`
+    v_ffbl_b32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`
+    v_floor_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_floor_f64_e64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_fma_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fma_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fract_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_fract_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fract_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fract_f64_e64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_frexp_exp_i16_f16_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f32_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
     v_frexp_exp_i32_f64_e64 :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`
-    v_frexp_mant_f16_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_frexp_mant_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f16_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_frexp_mant_f64_e64    :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_mov_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`param<amdgpu_synid8_param>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p1_f32_e64     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
@@ -1300,116 +1320,115 @@ VOP3
     v_interp_p1lv_f16       :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`f32<amdgpu_synid8_type_dev>`,           :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f16x2<amdgpu_synid8_type_dev>`   :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p2_f16         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`, :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid8_type_dev>`     :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
     v_interp_p2_f32_e64     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid8_attr>`::ref:`b32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`i16<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_ldexp_f32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`i32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f64             :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`i32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lerp_u8               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_2>`::ref:`b32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`
-    v_log_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_log_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_log_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lshlrev_b16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
-    v_lshlrev_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
-    v_lshlrev_b64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
-    v_lshrrev_b16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
-    v_lshrrev_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`
-    v_lshrrev_b64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
-    v_mac_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_mac_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i32_i24           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`::ref:`i32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i64_i32           :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src64_1>`::ref:`i64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_legacy_f32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_u16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u32_u24           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u64_u32           :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src64_1>`::ref:`u64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_max3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_max3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_max_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_max_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`i16<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f32             :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`i32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64             :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`i32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_4>`::ref:`b32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`
+    v_log_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_log_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshlrev_b16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_7>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_7>`
+    v_lshlrev_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_5>`
+    v_lshlrev_b64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
+    v_lshrrev_b16_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_7>`::ref:`u16<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_7>`
+    v_lshrrev_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_5>`
+    v_lshrrev_b64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src64_1>`
+    v_mac_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_mac_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_f32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`,       :ref:`src2<amdgpu_synid8_src32_7>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i24           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`::ref:`i32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i64_i32           :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src64_1>`::ref:`i64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f32        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_u16               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`,       :ref:`src2<amdgpu_synid8_src32_7>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u24           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u64_u32           :ref:`vdst<amdgpu_synid8_vdst64_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src64_1>`::ref:`u64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_max3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_max_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_max_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_i16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_max_i32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_max_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_max_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_mbcnt_hi_u32_b32      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_mbcnt_lo_u32_b32      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_med3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_med3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_min3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_min3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_min_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_min_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_max_i32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_max_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_max_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_mbcnt_hi_u32_b32      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_mbcnt_lo_u32_b32      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_med3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_med3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_min3_f32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_min3_u32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_min_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_min_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_i16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_min_i32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_min_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_min_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_mov_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
-    v_mov_fed_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
-    v_movreld_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
+    v_min_i16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_min_i32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_min_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_min_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_mov_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`
+    v_movreld_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`
     v_movrels_b32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
     v_movrelsd_b32_e64      :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`vsrc<amdgpu_synid8_vsrc32_0>`
-    v_mqsad_pk_u16_u8       :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mqsad_u32_u8          :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b128<amdgpu_synid8_type_dev>`,          :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc128_0>`::ref:`b128<amdgpu_synid8_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
-    v_msad_u8               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_2>`::ref:`b32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mul_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_mul_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mqsad_pk_u16_u8       :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mqsad_u32_u8          :ref:`vdst<amdgpu_synid8_vdst128_0>`::ref:`b128<amdgpu_synid8_type_dev>`,          :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`vsrc2<amdgpu_synid8_vsrc128_0>`::ref:`b128<amdgpu_synid8_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
+    v_msad_u8               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_4>`::ref:`b32<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_mul_f64               :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_mul_hi_i32_i24_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_mul_hi_u32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_mul_hi_u32_u24_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_mul_i32_i24_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_mul_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_u16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_mul_lo_u32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_mul_u32_u24_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_mul_hi_i32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_mul_hi_i32_i24_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_mul_hi_u32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_mul_hi_u32_u24_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_mul_i32_i24_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_legacy_f32_e64    :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`
+    v_mul_lo_u32            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_mul_u32_u24_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
     v_nop_e64
-    v_not_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`
-    v_or_b32_e64            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_perm_b32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`
-    v_qsad_pk_u16_u8        :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_3>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_rcp_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rcp_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_not_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`
+    v_or_b32_e64            :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
+    v_perm_b32              :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`
+    v_qsad_pk_u16_u8        :ref:`vdst<amdgpu_synid8_vdst64_0>`::ref:`b64<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`,    :ref:`src1<amdgpu_synid8_src32_5>`::ref:`b32<amdgpu_synid8_type_dev>`,   :ref:`src2<amdgpu_synid8_src64_1>`::ref:`b64<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rcp_f64_e64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_iflag_f32_e64     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64     :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_readlane_b32          :ref:`sdst<amdgpu_synid8_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid8_vsrc32_1>`,       :ref:`ssrc1<amdgpu_synid8_ssrc32_3>`
-    v_rndne_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rndne_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rndne_f64_e64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rsq_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rsq_f64_e64           :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_hi_u8             :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u8x4<amdgpu_synid8_type_dev>`,   :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u8x4<amdgpu_synid8_type_dev>`,  :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u16               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u16x2<amdgpu_synid8_type_dev>`,  :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u16x2<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`src2<amdgpu_synid8_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u8                :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_2>`::ref:`u8x4<amdgpu_synid8_type_dev>`,   :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u8x4<amdgpu_synid8_type_dev>`,  :ref:`src2<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sin_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_sin_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f16_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_sqrt_f32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8             :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_4>`::ref:`u8x4<amdgpu_synid8_type_dev>`,   :ref:`src1<amdgpu_synid8_src32_5>`::ref:`u8x4<amdgpu_synid8_type_dev>`,  :ref:`src2<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u16               :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_4>`::ref:`u16x2<amdgpu_synid8_type_dev>`,  :ref:`src1<amdgpu_synid8_src32_5>`::ref:`u16x2<amdgpu_synid8_type_dev>`, :ref:`src2<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u32               :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`src2<amdgpu_synid8_src32_5>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u8                :ref:`vdst<amdgpu_synid8_vdst32_0>`::ref:`u32<amdgpu_synid8_type_dev>`,           :ref:`src0<amdgpu_synid8_src32_4>`::ref:`u8x4<amdgpu_synid8_type_dev>`,   :ref:`src1<amdgpu_synid8_src32_5>`::ref:`u8x4<amdgpu_synid8_type_dev>`,  :ref:`src2<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f16_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_sqrt_f64_e64          :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_sub_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_subb_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
-    v_subbrev_u32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_3>`,        :ref:`src1<amdgpu_synid8_src32_3>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_f16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_f32_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_u16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_3>`,        :ref:`src1<amdgpu_synid8_src32_3>`
-    v_subrev_u32_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_3>`,        :ref:`src1<amdgpu_synid8_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_trig_preop_f64        :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_3>`::ref:`u32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_trunc_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_2>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_f16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_u16_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_6>`,        :ref:`src1<amdgpu_synid8_src32_7>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_u32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subb_u32_e64          :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_subbrev_u32_e64       :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_5>`,        :ref:`src1<amdgpu_synid8_src32_5>`,       :ref:`ssrc2<amdgpu_synid8_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f32_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_u16_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_7>`,        :ref:`src1<amdgpu_synid8_src32_7>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_u32_e64        :ref:`vdst<amdgpu_synid8_vdst32_0>`,      :ref:`sdst<amdgpu_synid8_sdst64_0>`,    :ref:`src0<amdgpu_synid8_src32_5>`,        :ref:`src1<amdgpu_synid8_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_trig_preop_f64        :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src0<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid8_src32_5>`::ref:`u32<amdgpu_synid8_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f16_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f32_e64         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src<amdgpu_synid8_src32_4>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_trunc_f64_e64         :ref:`vdst<amdgpu_synid8_vdst64_0>`,               :ref:`src<amdgpu_synid8_src64_1>`::ref:`m<amdgpu_synid8_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_writelane_b32         :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`ssrc0<amdgpu_synid8_ssrc32_4>`,       :ref:`ssrc1<amdgpu_synid8_ssrc32_3>`
-    v_xor_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_2>`,        :ref:`src1<amdgpu_synid8_src32_3>`
+    v_xor_b32_e64           :ref:`vdst<amdgpu_synid8_vdst32_0>`,               :ref:`src0<amdgpu_synid8_src32_4>`,        :ref:`src1<amdgpu_synid8_src32_5>`
 
 VOPC
 -----------------------
@@ -1428,12 +1447,12 @@ VOPC
     v_cmp_eq_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_eq_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_eq_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_eq_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_eq_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_eq_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_eq_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_eq_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_eq_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_eq_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1443,12 +1462,12 @@ VOPC
     v_cmp_f_f32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_f_f32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_f64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_f_i16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_f_i16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_f_i16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_i32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_f_i32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_i64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_f_u16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_f_u16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_f_u16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_u32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_f_u32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1458,12 +1477,12 @@ VOPC
     v_cmp_ge_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_ge_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_ge_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ge_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_ge_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_ge_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_ge_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ge_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_ge_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_ge_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1473,12 +1492,12 @@ VOPC
     v_cmp_gt_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_gt_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_gt_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_gt_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_gt_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_gt_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_gt_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_gt_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_gt_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_gt_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1488,12 +1507,12 @@ VOPC
     v_cmp_le_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_le_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_le_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_le_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_le_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_le_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_le_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_le_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_le_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_le_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1508,22 +1527,22 @@ VOPC
     v_cmp_lt_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_lt_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_lt_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_lt_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_lt_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_lt_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_lt_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_lt_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_lt_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_lt_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_u64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_ne_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ne_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_ne_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ne_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_ne_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ne_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_ne_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_ne_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_ne_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ne_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_ne_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1563,12 +1582,12 @@ VOPC
     v_cmp_o_f32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_o_f32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_o_f64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_t_i16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_t_i16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_t_i16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_t_i32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_t_i32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_t_i64                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmp_t_u16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmp_t_u16                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_t_u16_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_t_u32                    :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmp_t_u32_sdwa               :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1593,12 +1612,12 @@ VOPC
     v_cmpx_eq_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_eq_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_eq_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_eq_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_eq_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_eq_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_eq_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_eq_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_eq_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_eq_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1608,12 +1627,12 @@ VOPC
     v_cmpx_f_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_f_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_f_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_f_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_f_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_f_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_f_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_f_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_f_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_f_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1623,12 +1642,12 @@ VOPC
     v_cmpx_ge_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_ge_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_ge_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ge_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_ge_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_ge_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_ge_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ge_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_ge_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_ge_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1638,12 +1657,12 @@ VOPC
     v_cmpx_gt_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_gt_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_gt_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_gt_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_gt_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_gt_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_gt_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_gt_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_gt_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_gt_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1653,12 +1672,12 @@ VOPC
     v_cmpx_le_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_le_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_le_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_le_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_le_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_le_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_le_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_le_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_le_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_le_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1673,22 +1692,22 @@ VOPC
     v_cmpx_lt_f32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_lt_f32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_f64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_lt_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_lt_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_lt_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_lt_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_lt_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_lt_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_lt_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_lt_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_u64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_ne_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ne_i16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_ne_i16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ne_i32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_ne_i32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ne_i64                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_ne_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_ne_u16                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_ne_u16_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ne_u32                  :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_ne_u32_sdwa             :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1728,12 +1747,12 @@ VOPC
     v_cmpx_o_f32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_o_f32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_o_f64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_t_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_t_i16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_t_i16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_t_i32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_t_i32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_t_i64                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src64_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc64_0>`
-    v_cmpx_t_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
+    v_cmpx_t_u16                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_1>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_t_u16_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_t_u32                   :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`src0<amdgpu_synid8_src32_0>`,     :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`
     v_cmpx_t_u32_sdwa              :ref:`vcc<amdgpu_synid8_vcc_64>`,      :ref:`vsrc0<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`,  :ref:`vsrc1<amdgpu_synid8_vsrc32_0>`::ref:`m<amdgpu_synid8_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1788,6 +1807,7 @@ VOPC
     gfx8_data_mimg_store
     gfx8_data_mimg_store_d16
     gfx8_dst_buf_128
+    gfx8_dst_buf_32
     gfx8_dst_buf_64
     gfx8_dst_buf_96
     gfx8_dst_buf_d16_128
@@ -1821,6 +1841,10 @@ VOPC
     gfx8_src32_1
     gfx8_src32_2
     gfx8_src32_3
+    gfx8_src32_4
+    gfx8_src32_5
+    gfx8_src32_6
+    gfx8_src32_7
     gfx8_src64_0
     gfx8_src64_1
     gfx8_src_exp
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
index 9f17b34fc1a0..dc8d7e7d2a3a 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst
@@ -136,6 +136,7 @@ DS
     ds_read2_b64                   :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
     ds_read2st64_b32               :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b32x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
     ds_read2st64_b64               :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b64x2<amdgpu_synid9_type_dev>`, :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_read_addtid_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`                                           :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_read_b128                   :ref:`vdst<amdgpu_synid9_vdst128_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_read_b32                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_read_b64                    :ref:`vdst<amdgpu_synid9_vdst64_0>`,       :ref:`vaddr<amdgpu_synid9_addr_ds>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
@@ -168,6 +169,7 @@ DS
     ds_write2_b64                              :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
     ds_write2st64_b32                          :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata32_0>`,   :ref:`vdata1<amdgpu_synid9_vdata32_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
     ds_write2st64_b64                          :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata0<amdgpu_synid9_vdata64_0>`,   :ref:`vdata1<amdgpu_synid9_vdata64_0>`         :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>`
+    ds_write_addtid_b32                        :ref:`vdata<amdgpu_synid9_vdata32_0>`                              :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_write_b128                              :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata128_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_write_b16                               :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
     ds_write_b16_d16_hi                        :ref:`vaddr<amdgpu_synid9_addr_ds>`,    :ref:`vdata<amdgpu_synid9_vdata32_0>`                    :ref:`offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>`
@@ -332,7 +334,7 @@ MIMG
 .. parsed-literal::
 
     **INSTRUCTION**            **DST**      **SRC0**       **SRC1**     **SRC2**       **MODIFIERS**
-    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
     image_atomic_add                :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,   :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_atomic_and                :ref:`vdata<amdgpu_synid9_data_mimg_atomic_reg>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,   :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_atomic_cmpswap            :ref:`vdata<amdgpu_synid9_data_mimg_atomic_cmp>`::ref:`dst<amdgpu_synid9_ret>`, :ref:`vaddr<amdgpu_synid9_addr_mimg>`,   :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
@@ -370,59 +372,83 @@ MIMG
     image_gather4_lz       :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
     image_gather4_lz_o     :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
     image_gather4_o        :ref:`vdst<amdgpu_synid9_dst_mimg_gather4>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_get_lod          :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_get_resinfo      :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load             :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_load_mip         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_load_mip_pck     :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck         :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_load_pck_sgn     :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
-    image_sample           :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b_cl      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b_cl_o    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_b_o       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b_cl    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b_cl_o  :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_b_o     :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd_cl   :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cd_o    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cl      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_cl_o    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d_cl    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d_cl_o  :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_d_o     :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_l       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_l_o     :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_lz      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_lz_o    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_c_o       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd        :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd_cl     :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd_cl_o   :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cd_o      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cl        :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_cl_o      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d_cl      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d_cl_o    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_d_o       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_l         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_l_o       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_lz        :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_lz_o      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
-    image_sample_o         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_get_lod          :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_get_resinfo      :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load             :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_load_mip_pck     :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_mip_pck_sgn :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck         :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_load_pck_sgn     :ref:`vdst<amdgpu_synid9_dst_mimg_regular>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`               :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
+    image_sample           :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_cl_o    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_b_o       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_cl_o  :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_b_o     :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl   :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_cl_o :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cd_o    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_cl_o    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_cl_o  :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_d_o     :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_l_o     :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_lz_o    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_c_o       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd        :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl     :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_cl_o   :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cd_o      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl        :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_cl_o      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_cl_o    :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_d_o       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_l_o       :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz        :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_lz_o      :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
+    image_sample_o         :ref:`vdst<amdgpu_synid9_dst_mimg_regular_d16>`,    :ref:`vaddr<amdgpu_synid9_addr_mimg>`,     :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`,   :ref:`ssamp<amdgpu_synid9_samp_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
     image_store                     :ref:`vdata<amdgpu_synid9_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,   :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
     image_store_mip                 :ref:`vdata<amdgpu_synid9_data_mimg_store_d16>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,   :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>`
     image_store_mip_pck             :ref:`vdata<amdgpu_synid9_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,   :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
     image_store_pck                 :ref:`vdata<amdgpu_synid9_data_mimg_store>`,     :ref:`vaddr<amdgpu_synid9_addr_mimg>`,   :ref:`srsrc<amdgpu_synid9_rsrc_mimg>`      :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`a16<amdgpu_synid_a16>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>`
 
+MTBUF
+-----------------------
+
+.. parsed-literal::
+
+    **INSTRUCTION**                   **DST**   **SRC0**   **SRC1**   **SRC2**    **SRC3**      **MODIFIERS**
+    \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
+    tbuffer_load_format_d16_x     :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_d16_xy    :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_d16_xyz   :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_d16_xyzw  :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_x         :ref:`vdst<amdgpu_synid9_dst_buf_32>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_xy        :ref:`vdst<amdgpu_synid9_dst_buf_64>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_xyz       :ref:`vdst<amdgpu_synid9_dst_buf_96>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_load_format_xyzw      :ref:`vdst<amdgpu_synid9_dst_buf_128>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`, :ref:`soffset<amdgpu_synid9_offset_buf>`           :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_x          :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,  :ref:`soffset<amdgpu_synid9_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_xy         :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,  :ref:`soffset<amdgpu_synid9_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_xyz        :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,  :ref:`soffset<amdgpu_synid9_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_d16_xyzw       :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,  :ref:`soffset<amdgpu_synid9_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_x              :ref:`vdata<amdgpu_synid9_vdata32_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,  :ref:`soffset<amdgpu_synid9_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xy             :ref:`vdata<amdgpu_synid9_vdata64_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,  :ref:`soffset<amdgpu_synid9_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xyz            :ref:`vdata<amdgpu_synid9_vdata96_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,  :ref:`soffset<amdgpu_synid9_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+    tbuffer_store_format_xyzw           :ref:`vdata<amdgpu_synid9_vdata128_0>`, :ref:`vaddr<amdgpu_synid9_addr_buf>`, :ref:`srsrc<amdgpu_synid9_rsrc_buf>`,  :ref:`soffset<amdgpu_synid9_offset_buf>`   :ref:`fmt<amdgpu_synid_fmt>` :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>`
+
 MUBUF
 -----------------------
 
@@ -630,7 +656,6 @@ SOP1
     s_getpc_b64                    :ref:`sdst<amdgpu_synid9_sdst64_1>`
     s_mov_b32                      :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
     s_mov_b64                      :ref:`sdst<amdgpu_synid9_sdst64_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
-    s_mov_fed_b32                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
     s_movreld_b32                  :ref:`sdst<amdgpu_synid9_sdst32_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_0>`
     s_movreld_b64                  :ref:`sdst<amdgpu_synid9_sdst64_0>`,     :ref:`ssrc<amdgpu_synid9_ssrc64_0>`
     s_movrels_b32                  :ref:`sdst<amdgpu_synid9_sdst32_1>`,     :ref:`ssrc<amdgpu_synid9_ssrc32_1>`
@@ -850,12 +875,12 @@ VOP1
     v_cvt_f16_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
     v_cvt_f16_f32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_cvt_f16_f32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_i16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f16_i16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_1>`
     v_cvt_f16_i16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f16_i16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_cvt_f16_u16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
+    v_cvt_f16_i16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_u16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_1>`
     v_cvt_f16_u16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_f16_u16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_f16_u16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_f32_f16                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
     v_cvt_f32_f16_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_cvt_f32_f16_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
@@ -893,10 +918,10 @@ VOP1
     v_cvt_i32_f64                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src64_0>`
     v_cvt_norm_i16_f16              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
     v_cvt_norm_i16_f16_dpp          :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_norm_i16_f16_sdwa         :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_norm_i16_f16_sdwa         :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_norm_u16_f16              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
     v_cvt_norm_u16_f16_dpp          :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_cvt_norm_u16_f16_sdwa         :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
+    v_cvt_norm_u16_f16_sdwa         :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_cvt_off_f32_i4                :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
     v_cvt_off_f32_i4_dpp            :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_cvt_off_f32_i4_sdwa           :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
@@ -968,9 +993,6 @@ VOP1
     v_mov_b32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
     v_mov_b32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_mov_b32_sdwa                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
-    v_mov_fed_b32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
-    v_mov_fed_b32_dpp               :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mov_fed_b32_sdwa              :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>`
     v_nop
     v_not_b32                       :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`src<amdgpu_synid9_src32_0>`
     v_not_b32_dpp                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,     :ref:`vsrc<amdgpu_synid9_vsrc32_0>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
@@ -1044,9 +1066,9 @@ VOP2
     v_add_f32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_add_f32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_add_f32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_add_u16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_add_u16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_add_u16_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_add_u16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_add_u16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_add_u32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_add_u32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_add_u32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1056,30 +1078,30 @@ VOP2
     v_and_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_and_b32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_and_b32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_ashrrev_i16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_ashrrev_i16_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ashrrev_i16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_ashrrev_i32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_ashrrev_i16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_ashrrev_i32_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_ashrrev_i32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_ashrrev_i32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cndmask_b32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
     v_cndmask_b32_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_cndmask_b32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_ldexp_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`i16<amdgpu_synid9_type_dev>`
     v_ldexp_f16_dpp       :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`i16<amdgpu_synid9_type_dev>`         :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_ldexp_f16_sdwa      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`i16<amdgpu_synid9_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshlrev_b16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_lshlrev_b16_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshlrev_b16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshlrev_b32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshlrev_b16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshlrev_b32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_lshlrev_b32_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshlrev_b32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshlrev_b32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u16<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_lshrrev_b16_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u16<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshrrev_b16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_lshrrev_b32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_lshrrev_b16_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u16<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b32         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_lshrrev_b32_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,  :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_lshrrev_b32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_lshrrev_b32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`::ref:`u32<amdgpu_synid9_type_dev>`, :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_mac_f16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_mac_f16_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_mac_f32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
@@ -1094,15 +1116,15 @@ VOP2
     v_max_f32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_max_f32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_max_f32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_i16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_max_i16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_max_i16_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_i16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_i16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_max_i32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_max_i32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_max_i32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_max_u16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_max_u16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_max_u16_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_max_u16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_max_u16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_max_u32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_max_u32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_max_u32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1112,15 +1134,15 @@ VOP2
     v_min_f32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_min_f32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_min_f32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_i16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_min_i16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_min_i16_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_i16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_i16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_min_i32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_min_i32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_min_i32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_min_u16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_min_u16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_min_u16_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_min_u16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_min_u16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_min_u32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_min_u32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_min_u32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1142,9 +1164,9 @@ VOP2
     v_mul_legacy_f32      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_mul_legacy_f32_dpp  :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_mul_legacy_f32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_mul_lo_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_mul_lo_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_mul_lo_u16_dpp      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_mul_lo_u16_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_mul_lo_u16_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_mul_u32_u24         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_mul_u32_u24_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_mul_u32_u24_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1160,33 +1182,33 @@ VOP2
     v_sub_f32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_sub_f32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_sub_f32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_sub_u16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_sub_u16             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_sub_u16_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_sub_u16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_sub_u16_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_sub_u32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_sub_u32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_sub_u32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_subb_co_u32         :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
     v_subb_co_u32_dpp     :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_subb_co_u32_sdwa    :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subbrev_co_u32      :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
+    v_subbrev_co_u32      :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_3>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`
     v_subbrev_co_u32_dpp  :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_co_u32       :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subbrev_co_u32_sdwa :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,    :ref:`vcc<amdgpu_synid9_vcc_64>`   :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_co_u32       :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_3>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_subrev_co_u32_dpp   :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_co_u32_sdwa  :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_co_u32_sdwa  :ref:`vdst<amdgpu_synid9_vdst32_0>`, :ref:`vcc<amdgpu_synid9_vcc_64>`, :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_subrev_f16_dpp      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_f16_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_f32          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_f16_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_f32          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_subrev_f32_dpp      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,    :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_f32_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_f32_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_subrev_u16_dpp      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_u16_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
-    v_subrev_u32          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_subrev_u16_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u32          :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_subrev_u32_dpp      :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
-    v_subrev_u32_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_subrev_u32_sdwa     :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_xor_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`,       :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_xor_b32_dpp         :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`,      :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`             :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>`
     v_xor_b32_sdwa        :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`           :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
@@ -1198,302 +1220,302 @@ VOP3
 
     **INSTRUCTION**                    **DST0**       **DST1**     **SRC0**         **SRC1**        **SRC2**            **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_add3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_add_co_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_add_co_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_add_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_add_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_add_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_add_lshl_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_add_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_add_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_addc_co_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
-    v_alignbit_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_alignbyte_b32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_and_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_and_or_b32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_ashrrev_i16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
-    v_ashrrev_i32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
-    v_ashrrev_i64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
-    v_bcnt_u32_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_bfe_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`
-    v_bfe_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_bfi_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_bfm_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_bfrev_b32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
-    v_ceil_f16_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_ceil_f32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_add_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_lshl_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_add_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_add_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_addc_co_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_alignbit_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_alignbyte_b32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_and_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_and_or_b32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_ashrrev_i16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_7>`
+    v_ashrrev_i32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_5>`
+    v_ashrrev_i64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
+    v_bcnt_u32_b32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_bfe_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`
+    v_bfe_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_bfi_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_bfm_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_bfrev_b32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`
+    v_ceil_f16_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ceil_f32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_ceil_f64_e64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_clrexcp_e64
-    v_cmp_class_f16_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmp_class_f32_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmp_class_f64_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmp_eq_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_eq_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_class_f16_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_class_f32_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_class_f64_e64            :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmp_eq_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_eq_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_eq_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_eq_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_eq_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_eq_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_eq_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_eq_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_eq_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_eq_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_eq_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_eq_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_eq_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_f_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_f_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_f_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_f_f64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_f_i16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_f_i32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_f_i16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_f_i32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_f_i64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_f_u16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_f_u32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_f_u16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_f_u32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_f_u64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_ge_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ge_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ge_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_ge_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ge_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_ge_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_ge_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_ge_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_ge_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_ge_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_ge_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_ge_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_ge_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_ge_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_gt_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_gt_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_gt_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_gt_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_gt_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_gt_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_gt_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_gt_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_gt_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_gt_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_gt_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_gt_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_gt_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_gt_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_le_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_le_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_le_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_le_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_le_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_le_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_le_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_le_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_le_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_le_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_le_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_le_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_le_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_le_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_lg_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lg_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lg_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_lg_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_lt_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_lt_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_lt_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_lt_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_lt_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_lt_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_lt_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_lt_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_lt_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_lt_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_lt_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_lt_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_ne_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_ne_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_ne_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_ne_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_ne_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_ne_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_ne_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_ne_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_ne_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_ne_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_neq_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_neq_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_neq_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_neq_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nge_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nge_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nge_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nge_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ngt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_ngt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_ngt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_ngt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nle_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nle_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nle_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nle_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlg_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlg_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlg_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nlg_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_nlt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_nlt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_nlt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_o_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_o_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_o_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_o_f64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_t_i16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_t_i32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_t_i16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_t_i32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_t_i64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_t_u16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmp_t_u32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmp_t_u16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmp_t_u32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmp_t_u64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmp_tru_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_tru_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_tru_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_tru_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_u_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmp_u_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f16_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmp_u_f32_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmp_u_f64_e64                :ref:`sdst<amdgpu_synid9_sdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_class_f16_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmpx_class_f32_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmpx_class_f64_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_cmpx_eq_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_eq_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_class_f16_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_class_f32_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_class_f64_e64           :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_cmpx_eq_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_eq_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_eq_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_eq_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_eq_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_eq_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_eq_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_eq_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_eq_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_eq_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_eq_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_eq_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_eq_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_f_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_f_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_f_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_f_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_f_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_f_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_f_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_f_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_f_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_f_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_f_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_f_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_f_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_f_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_ge_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ge_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ge_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_ge_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ge_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_ge_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_ge_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_ge_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_ge_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_ge_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_ge_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_ge_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_ge_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_ge_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_gt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_gt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_gt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_gt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_gt_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_gt_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_gt_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_gt_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_gt_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_gt_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_gt_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_gt_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_gt_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_gt_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_le_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_le_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_le_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_le_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_le_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_le_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_le_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_le_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_le_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_le_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_le_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_le_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_le_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_le_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_lg_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lg_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lg_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_lg_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_lt_f32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_lt_f64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_lt_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_lt_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_lt_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_lt_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_lt_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_lt_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_lt_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_lt_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_lt_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_lt_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_ne_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_ne_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_ne_i16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_ne_i32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_ne_i64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_ne_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_ne_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_ne_u16_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_ne_u32_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_ne_u64_e64              :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_neq_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_neq_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_neq_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_neq_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nge_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nge_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nge_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nge_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ngt_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_ngt_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_ngt_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_ngt_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nle_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nle_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nle_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nle_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlg_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlg_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlg_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nlg_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlt_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_nlt_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_nlt_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_nlt_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_o_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_o_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_o_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_o_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_t_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_t_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_t_i16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_t_i32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_t_i64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_t_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cmpx_t_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_cmpx_t_u16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_cmpx_t_u32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
     v_cmpx_t_u64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`
-    v_cmpx_tru_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_tru_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f16_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_tru_f32_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_tru_f64_e64             :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_u_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cmpx_u_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f16_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cmpx_u_f32_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
     v_cmpx_u_f64_e64               :ref:`sdst<amdgpu_synid9_sdst64_1>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cndmask_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
-    v_cos_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cos_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubeid_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubema_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubesc_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cubetc_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f16_i16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_f16_u16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_f32_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cndmask_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`
+    v_cos_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cos_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubeid_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubema_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubesc_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cubetc_f32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f16_i16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_6>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f16_u16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_6>`                                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_cvt_f32_f64_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_i32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte0_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte1_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte2_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f32_ubyte3_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_f32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_i32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_f64_u32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_flr_i32_f32_e64          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_i16_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_i32_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_f32_i32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte0_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte1_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte2_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f32_ubyte3_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_f32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_i32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_f64_u32_e64              :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_flr_i32_f32_e64          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_i16_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_i32_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
     v_cvt_i32_f64_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_norm_i16_f16_e64         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_norm_u16_f16_e64         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_off_f32_i4_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_cvt_pk_i16_i32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cvt_pk_u16_u32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_cvt_pk_u8_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`
-    v_cvt_pkaccum_u8_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`
-    v_cvt_pknorm_i16_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_cvt_pknorm_i16_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_pknorm_u16_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_cvt_pknorm_u16_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_rpi_i32_f32_e64          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_cvt_u16_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_cvt_u32_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_norm_i16_f16_e64         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_norm_u16_f16_e64         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_off_f32_i4_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`                                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_cvt_pk_i16_i32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_cvt_pk_u16_u32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_cvt_pk_u8_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`
+    v_cvt_pkaccum_u8_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`
+    v_cvt_pknorm_i16_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_cvt_pknorm_i16_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_pknorm_u16_f16           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_cvt_pknorm_u16_f32           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_pkrtz_f16_f32            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_rpi_i32_f32_e64          :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_cvt_u16_f16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_cvt_u32_f32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
     v_cvt_u32_f64_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_div_fixup_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_div_fixup_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fixup_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fixup_f64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_fixup_legacy_f16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_div_fmas_f32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_div_fixup_legacy_f16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_div_fmas_f32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_div_fmas_f64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_div_scale_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`,     :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
+    v_div_scale_f32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`,     :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
     v_div_scale_f64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`vcc<amdgpu_synid9_vcc_64>`,     :ref:`src0<amdgpu_synid9_src64_1>`,        :ref:`src1<amdgpu_synid9_src64_1>`,       :ref:`src2<amdgpu_synid9_src64_1>`
-    v_exp_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_exp_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_exp_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ffbh_i32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
-    v_ffbh_u32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
-    v_ffbl_b32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
-    v_floor_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_floor_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_exp_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_exp_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ffbh_i32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`
+    v_ffbh_u32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`
+    v_ffbl_b32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`
+    v_floor_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_floor_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_floor_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_fma_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_fma_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fma_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_fma_legacy_f16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_fract_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_fract_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_fma_legacy_f16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_fract_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_fract_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_frexp_exp_i16_f16_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_frexp_exp_i32_f32_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_frexp_exp_i16_f16_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
+    v_frexp_exp_i32_f32_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
     v_frexp_exp_i32_f64_e64        :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`
-    v_frexp_mant_f16_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_frexp_mant_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_frexp_mant_f16_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_frexp_mant_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_frexp_mant_f64_e64           :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_mov_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`param<amdgpu_synid9_param>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p1_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
@@ -1502,138 +1524,137 @@ VOP3
     v_interp_p2_f16                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`     :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
     v_interp_p2_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_interp_p2_legacy_f16         :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`, :ref:`attr<amdgpu_synid9_attr>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`::ref:`f32<amdgpu_synid9_type_dev>`     :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_ldexp_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`i16<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_ldexp_f32                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_ldexp_f64                    :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lerp_u8                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_2>`::ref:`b32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`
-    v_log_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_log_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_log_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_lshl_add_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_lshl_or_b32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_3>`
-    v_lshlrev_b16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
-    v_lshlrev_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
-    v_lshlrev_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
-    v_lshrrev_b16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
-    v_lshrrev_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`
-    v_lshrrev_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
-    v_mac_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_mac_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i32_i16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i32_i24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`::ref:`i32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_i64_i32                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src64_1>`::ref:`i64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_legacy_f16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_legacy_f32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mad_legacy_i16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_legacy_u16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u32_u16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u32_u24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mad_u64_u32                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src64_1>`::ref:`u64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_max3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_max3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_max3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_max3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_max3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_max_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_max_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`i16<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_ldexp_f32                    :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`i32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_ldexp_f64                    :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`i32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lerp_u8                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_4>`::ref:`b32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`
+    v_log_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_log_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_log_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_lshl_add_u32                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_lshl_or_b32                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_5>`
+    v_lshlrev_b16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_7>`
+    v_lshlrev_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_5>`
+    v_lshlrev_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
+    v_lshrrev_b16_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_7>`
+    v_lshrrev_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_5>`
+    v_lshrrev_b64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src64_1>`
+    v_mac_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_mac_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_f16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_f32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_7>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_5>`::ref:`i32<amdgpu_synid9_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i32_i24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`::ref:`i32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_i64_i32                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src64_1>`::ref:`i64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_f32               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mad_legacy_i16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_7>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_legacy_u16               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_7>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_7>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u16                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u32_u24                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mad_u64_u32                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src64_1>`::ref:`u64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_max3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_7>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_max3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_max3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_7>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_max3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_max_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_max_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_max_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_max_i16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_max_i32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_max_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_max_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_mbcnt_hi_u32_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_mbcnt_lo_u32_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_med3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_med3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_med3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_med3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_med3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_med3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_min3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_min3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_min3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_min3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_min3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_min_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_min_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_max_i16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_max_i32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_max_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_max_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_mbcnt_hi_u32_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_mbcnt_lo_u32_b32             :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_med3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_med3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_med3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_7>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_med3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_med3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_7>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_med3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_min3_f16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_min3_f32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,     :ref:`src2<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`          :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min3_i16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_7>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_min3_i32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_min3_u16                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`,       :ref:`src2<amdgpu_synid9_src32_7>`            :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_min3_u32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_min_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_min_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_min_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_min_i16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_min_i32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_min_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_min_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_mov_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
-    v_mov_fed_b32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
-    v_mqsad_pk_u16_u8              :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mqsad_u32_u8                 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b128<amdgpu_synid9_type_dev>`,          :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc128_0>`::ref:`b128<amdgpu_synid9_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
-    v_msad_u8                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_2>`::ref:`b32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_mul_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_mul_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_min_i16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_min_i32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_min_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_min_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_mov_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`
+    v_mqsad_pk_u16_u8              :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mqsad_u32_u8                 :ref:`vdst<amdgpu_synid9_vdst128_0>`::ref:`b128<amdgpu_synid9_type_dev>`,          :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`vsrc2<amdgpu_synid9_vsrc128_0>`::ref:`b128<amdgpu_synid9_type_dev>`      :ref:`clamp<amdgpu_synid_clamp>`
+    v_msad_u8                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_4>`::ref:`b32<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_mul_f64                      :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_hi_i32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_mul_hi_i32_i24_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_mul_hi_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_mul_hi_u32_u24_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_mul_i32_i24_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_mul_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_mul_lo_u16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_mul_lo_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_mul_u32_u24_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_mul_hi_i32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_mul_hi_i32_i24_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_mul_hi_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_mul_hi_u32_u24_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_mul_i32_i24_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_mul_legacy_f32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_mul_lo_u16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`
+    v_mul_lo_u32                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_mul_u32_u24_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
     v_nop_e64
-    v_not_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
-    v_or3_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_or_b32_e64                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_pack_b32_f16                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
-    v_perm_b32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_qsad_pk_u16_u8               :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_3>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_rcp_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rcp_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_not_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`
+    v_or3_b32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_or_b32_e64                   :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
+    v_pack_b32_f16                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`op_sel<amdgpu_synid_vop3_op_sel>`
+    v_perm_b32                     :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_qsad_pk_u16_u8               :ref:`vdst<amdgpu_synid9_vdst64_0>`::ref:`b64<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`,    :ref:`src1<amdgpu_synid9_src32_5>`::ref:`b32<amdgpu_synid9_type_dev>`,   :ref:`src2<amdgpu_synid9_src64_1>`::ref:`b64<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rcp_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rcp_f64_e64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rcp_iflag_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rcp_iflag_f32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_readlane_b32                 :ref:`sdst<amdgpu_synid9_sdst32_2>`,               :ref:`vsrc0<amdgpu_synid9_vsrc32_1>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
-    v_rndne_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rndne_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rndne_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rndne_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rndne_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_rsq_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_rsq_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_rsq_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_rsq_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_rsq_f64_e64                  :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sad_hi_u8                    :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u8x4<amdgpu_synid9_type_dev>`,   :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u8x4<amdgpu_synid9_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u16x2<amdgpu_synid9_type_dev>`,  :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`            :ref:`clamp<amdgpu_synid_clamp>`
-    v_sad_u8                       :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_2>`::ref:`u8x4<amdgpu_synid9_type_dev>`,   :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u8x4<amdgpu_synid9_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sat_pk_u8_i16_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
-    v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`
-    v_sin_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_sin_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sqrt_f16_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_sqrt_f32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sad_hi_u8                    :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_4>`::ref:`u8x4<amdgpu_synid9_type_dev>`,   :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u8x4<amdgpu_synid9_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_4>`::ref:`u16x2<amdgpu_synid9_type_dev>`,  :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`            :ref:`clamp<amdgpu_synid_clamp>`
+    v_sad_u8                       :ref:`vdst<amdgpu_synid9_vdst32_0>`::ref:`u32<amdgpu_synid9_type_dev>`,           :ref:`src0<amdgpu_synid9_src32_4>`::ref:`u8x4<amdgpu_synid9_type_dev>`,   :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u8x4<amdgpu_synid9_type_dev>`,  :ref:`src2<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sat_pk_u8_i16_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`
+    v_screen_partition_4se_b32_e64 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`
+    v_sin_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sin_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sqrt_f16_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_sqrt_f32_e64                 :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_sqrt_f64_e64                 :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_co_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_sub_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_sub_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_sub_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_sub_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_subb_co_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
-    v_subbrev_co_u32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_3>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_co_u32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_3>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_f16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
-    v_subrev_f32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_subrev_u16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`,        :ref:`src1<amdgpu_synid9_src32_3>`
-    v_subrev_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_3>`,        :ref:`src1<amdgpu_synid9_src32_3>`                        :ref:`clamp<amdgpu_synid_clamp>`
-    v_trig_preop_f64               :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_3>`::ref:`u32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
-    v_trunc_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
-    v_trunc_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_2>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_co_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_f32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_sub_i16                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`                        :ref:`op_sel<amdgpu_synid_vop3_op_sel>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_i32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_u16_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_6>`,        :ref:`src1<amdgpu_synid9_src32_7>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_sub_u32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subb_co_u32_e64              :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_subbrev_co_u32_e64           :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_5>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`ssrc2<amdgpu_synid9_ssrc64_1>`           :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_co_u32_e64            :ref:`vdst<amdgpu_synid9_vdst32_0>`,      :ref:`sdst<amdgpu_synid9_sdst64_0>`,    :ref:`src0<amdgpu_synid9_src32_5>`,        :ref:`src1<amdgpu_synid9_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_f32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                      :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_subrev_u16_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_7>`,        :ref:`src1<amdgpu_synid9_src32_7>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_subrev_u32_e64               :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_5>`,        :ref:`src1<amdgpu_synid9_src32_5>`                        :ref:`clamp<amdgpu_synid_clamp>`
+    v_trig_preop_f64               :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src0<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`,      :ref:`src1<amdgpu_synid9_src32_5>`::ref:`u32<amdgpu_synid9_type_dev>`                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
+    v_trunc_f16_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>`
+    v_trunc_f32_e64                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src<amdgpu_synid9_src32_4>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_trunc_f64_e64                :ref:`vdst<amdgpu_synid9_vdst64_0>`,               :ref:`src<amdgpu_synid9_src64_1>`::ref:`m<amdgpu_synid9_mod_vop3_abs_neg>`                                    :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
     v_writelane_b32                :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`ssrc0<amdgpu_synid9_ssrc32_4>`,       :ref:`ssrc1<amdgpu_synid9_ssrc32_3>`
-    v_xad_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`,       :ref:`src2<amdgpu_synid9_src32_3>`
-    v_xor_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_2>`,        :ref:`src1<amdgpu_synid9_src32_3>`
+    v_xad_u32                      :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`,       :ref:`src2<amdgpu_synid9_src32_5>`
+    v_xor_b32_e64                  :ref:`vdst<amdgpu_synid9_vdst32_0>`,               :ref:`src0<amdgpu_synid9_src32_4>`,        :ref:`src1<amdgpu_synid9_src32_5>`
 
 VOP3P
 -----------------------
@@ -1642,25 +1663,25 @@ VOP3P
 
     **INSTRUCTION**           **DST**      **SRC0**        **SRC1**     **SRC2**       **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
-    v_pk_add_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_add_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_ashrrev_i16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_fma_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`,    :ref:`src2<amdgpu_synid9_src32_3>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_lshlrev_b16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_lshrrev_b16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_3>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_mad_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`,    :ref:`src2<amdgpu_synid9_src32_3>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_mad_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`,    :ref:`src2<amdgpu_synid9_src32_3>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_max_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_max_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_max_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_min_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_min_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_min_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_mul_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_mul_lo_u16       :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
-    v_pk_sub_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_pk_sub_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_2>`,       :ref:`src1<amdgpu_synid9_src32_3>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,       :ref:`src1<amdgpu_synid9_src32_5>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_add_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_ashrrev_i16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_fma_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,       :ref:`src1<amdgpu_synid9_src32_5>`,    :ref:`src2<amdgpu_synid9_src32_5>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_lshlrev_b16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_lshrrev_b16      :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_7>`::ref:`u16x2<amdgpu_synid9_type_dev>`, :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mad_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`,    :ref:`src2<amdgpu_synid9_src32_7>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mad_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`,    :ref:`src2<amdgpu_synid9_src32_7>`       :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,       :ref:`src1<amdgpu_synid9_src32_5>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_max_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_max_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,       :ref:`src1<amdgpu_synid9_src32_5>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_min_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_min_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_mul_f16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_4>`,       :ref:`src1<amdgpu_synid9_src32_5>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_mul_lo_u16       :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>`
+    v_pk_sub_i16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
+    v_pk_sub_u16          :ref:`vdst<amdgpu_synid9_vdst32_0>`,    :ref:`src0<amdgpu_synid9_src32_6>`,       :ref:`src1<amdgpu_synid9_src32_7>`                :ref:`op_sel<amdgpu_synid_op_sel>` :ref:`op_sel_hi<amdgpu_synid_op_sel_hi>` :ref:`clamp<amdgpu_synid_clamp>`
 
 VOPC
 -----------------------
@@ -1679,13 +1700,13 @@ VOPC
     v_cmp_eq_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_eq_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_eq_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_eq_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_eq_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_eq_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_eq_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_eq_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_eq_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_eq_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_eq_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_eq_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1694,13 +1715,13 @@ VOPC
     v_cmp_f_f32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_f_f32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_f64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_f_i16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_f_i16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_i16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_f_i16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_i32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_f_i32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_i64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_f_u16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_f_u16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_f_u16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_f_u16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_u32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_f_u32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_f_u64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1709,13 +1730,13 @@ VOPC
     v_cmp_ge_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_ge_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_ge_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_ge_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ge_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_ge_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_ge_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_ge_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ge_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ge_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_ge_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ge_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1724,13 +1745,13 @@ VOPC
     v_cmp_gt_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_gt_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_gt_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_gt_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_gt_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_gt_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_gt_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_gt_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_gt_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_gt_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_gt_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_gt_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1739,13 +1760,13 @@ VOPC
     v_cmp_le_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_le_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_le_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_le_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_le_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_le_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_le_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_le_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_le_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_le_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_le_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_le_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1759,23 +1780,23 @@ VOPC
     v_cmp_lt_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_lt_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_lt_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_lt_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_lt_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_lt_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_lt_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_lt_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_lt_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_lt_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_lt_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_lt_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_ne_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_ne_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ne_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ne_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_ne_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ne_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_ne_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_ne_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_ne_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_ne_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ne_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_ne_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_ne_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1814,13 +1835,13 @@ VOPC
     v_cmp_o_f32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_o_f32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_o_f64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_t_i16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_t_i16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_i16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_t_i16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_t_i32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_t_i32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_t_i64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmp_t_u16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmp_t_u16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmp_t_u16                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmp_t_u16_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_t_u32                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmp_t_u32_sdwa               :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmp_t_u64                    :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1844,13 +1865,13 @@ VOPC
     v_cmpx_eq_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_eq_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_eq_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_eq_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_eq_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_eq_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_eq_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_eq_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_eq_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_eq_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_eq_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_eq_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1859,13 +1880,13 @@ VOPC
     v_cmpx_f_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_f_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_f_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_f_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_f_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_f_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_f_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_f_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_f_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_f_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_f_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_f_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1874,13 +1895,13 @@ VOPC
     v_cmpx_ge_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_ge_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_ge_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_ge_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ge_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_ge_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_ge_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_ge_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ge_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ge_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_ge_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ge_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1889,13 +1910,13 @@ VOPC
     v_cmpx_gt_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_gt_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_gt_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_gt_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_gt_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_gt_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_gt_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_gt_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_gt_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_gt_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_gt_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_gt_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1904,13 +1925,13 @@ VOPC
     v_cmpx_le_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_le_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_le_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_le_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_le_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_le_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_le_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_le_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_le_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_le_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_le_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_le_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1924,23 +1945,23 @@ VOPC
     v_cmpx_lt_f32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_lt_f32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_f64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_lt_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_lt_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_lt_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_lt_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_lt_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_lt_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_lt_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_lt_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_lt_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_lt_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_ne_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_ne_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_i16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ne_i16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ne_i32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_ne_i32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ne_i64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_ne_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_ne_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_ne_u16                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_ne_u16_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ne_u32                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_ne_u32_sdwa             :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_ne_u64                  :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -1979,13 +2000,13 @@ VOPC
     v_cmpx_o_f32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_o_f32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_dpp_sdwa_abs_neg>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_o_f64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_t_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_t_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_i16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_t_i16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_t_i32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_t_i32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_t_i64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
-    v_cmpx_t_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
-    v_cmpx_t_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
+    v_cmpx_t_u16                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
+    v_cmpx_t_u16_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_1>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_t_u32                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`
     v_cmpx_t_u32_sdwa              :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`,   :ref:`vsrc1<amdgpu_synid9_vsrc32_0>`::ref:`m<amdgpu_synid9_mod_sdwa_sext>`          :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>`
     v_cmpx_t_u64                   :ref:`vcc<amdgpu_synid9_vcc_64>`,      :ref:`src0<amdgpu_synid9_src64_0>`,     :ref:`vsrc1<amdgpu_synid9_vsrc64_0>`
@@ -2071,6 +2092,10 @@ VOPC
     gfx9_src32_1
     gfx9_src32_2
     gfx9_src32_3
+    gfx9_src32_4
+    gfx9_src32_5
+    gfx9_src32_6
+    gfx9_src32_7
     gfx9_src64_0
     gfx9_src64_1
     gfx9_src_exp
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst
index 385917d6a7b8..7cb3c38bd356 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst
@@ -64,8 +64,8 @@ VOP3P
     **INSTRUCTION**                    **DST**       **SRC0**        **SRC1**        **SRC2**           **MODIFIERS**
     \ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
     v_dot2_f32_f16                 :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`f16x2<amdgpu_synid906_type_dev>`, :ref:`src1<amdgpu_synid906_src32_2>`::ref:`f16x2<amdgpu_synid906_type_dev>`, :ref:`src2<amdgpu_synid906_src32_2>`::ref:`f32<amdgpu_synid906_type_dev>`       :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_i32_i16                 :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`i16x2<amdgpu_synid906_type_dev>`, :ref:`src1<amdgpu_synid906_src32_2>`::ref:`i16x2<amdgpu_synid906_type_dev>`, :ref:`src2<amdgpu_synid906_src32_2>`::ref:`i32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_u32_u16                 :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`u16x2<amdgpu_synid906_type_dev>`, :ref:`src1<amdgpu_synid906_src32_2>`::ref:`u16x2<amdgpu_synid906_type_dev>`, :ref:`src2<amdgpu_synid906_src32_2>`::ref:`u32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_i32_i16                 :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_3>`::ref:`i16x2<amdgpu_synid906_type_dev>`, :ref:`src1<amdgpu_synid906_src32_4>`::ref:`i16x2<amdgpu_synid906_type_dev>`, :ref:`src2<amdgpu_synid906_src32_2>`::ref:`i32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_u32_u16                 :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_3>`::ref:`u16x2<amdgpu_synid906_type_dev>`, :ref:`src1<amdgpu_synid906_src32_4>`::ref:`u16x2<amdgpu_synid906_type_dev>`, :ref:`src2<amdgpu_synid906_src32_2>`::ref:`u32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_i32_i8                  :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`i8x4<amdgpu_synid906_type_dev>`,  :ref:`src1<amdgpu_synid906_src32_2>`::ref:`i8x4<amdgpu_synid906_type_dev>`,  :ref:`src2<amdgpu_synid906_src32_2>`::ref:`i32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_u32_u8                  :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`u8x4<amdgpu_synid906_type_dev>`,  :ref:`src1<amdgpu_synid906_src32_2>`::ref:`u8x4<amdgpu_synid906_type_dev>`,  :ref:`src2<amdgpu_synid906_src32_2>`::ref:`u32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot8_i32_i4                  :ref:`vdst<amdgpu_synid906_vdst32_0>`,     :ref:`src0<amdgpu_synid906_src32_1>`::ref:`i4x8<amdgpu_synid906_type_dev>`,  :ref:`src1<amdgpu_synid906_src32_2>`::ref:`i4x8<amdgpu_synid906_type_dev>`,  :ref:`src2<amdgpu_synid906_src32_2>`::ref:`i32<amdgpu_synid906_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
@@ -84,6 +84,8 @@ VOP3P
     gfx906_src32_0
     gfx906_src32_1
     gfx906_src32_2
+    gfx906_src32_3
+    gfx906_src32_4
     gfx906_vdst32_0
     gfx906_vsrc32_0
     gfx906_mad_type_dev
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst
index 27da01792895..979c0f2d1738 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst
@@ -95,8 +95,8 @@ VOP3P
     v_accvgpr_read_b32     :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`asrc<amdgpu_synid908_asrc32_0>`
     v_accvgpr_write_b32    :ref:`adst<amdgpu_synid908_adst32_0>`,        :ref:`src<amdgpu_synid908_src32_3>`
     v_dot2_f32_f16         :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`f16x2<amdgpu_synid908_type_dev>`,    :ref:`src1<amdgpu_synid908_src32_2>`::ref:`f16x2<amdgpu_synid908_type_dev>`,    :ref:`src2<amdgpu_synid908_src32_2>`::ref:`f32<amdgpu_synid908_type_dev>`       :ref:`neg_lo<amdgpu_synid_neg_lo>` :ref:`neg_hi<amdgpu_synid_neg_hi>` :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_i32_i16         :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`i16x2<amdgpu_synid908_type_dev>`,    :ref:`src1<amdgpu_synid908_src32_2>`::ref:`i16x2<amdgpu_synid908_type_dev>`,    :ref:`src2<amdgpu_synid908_src32_2>`::ref:`i32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
-    v_dot2_u32_u16         :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`u16x2<amdgpu_synid908_type_dev>`,    :ref:`src1<amdgpu_synid908_src32_2>`::ref:`u16x2<amdgpu_synid908_type_dev>`,    :ref:`src2<amdgpu_synid908_src32_2>`::ref:`u32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_i32_i16         :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_4>`::ref:`i16x2<amdgpu_synid908_type_dev>`,    :ref:`src1<amdgpu_synid908_src32_5>`::ref:`i16x2<amdgpu_synid908_type_dev>`,    :ref:`src2<amdgpu_synid908_src32_2>`::ref:`i32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
+    v_dot2_u32_u16         :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_4>`::ref:`u16x2<amdgpu_synid908_type_dev>`,    :ref:`src1<amdgpu_synid908_src32_5>`::ref:`u16x2<amdgpu_synid908_type_dev>`,    :ref:`src2<amdgpu_synid908_src32_2>`::ref:`u32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_i32_i8          :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`i8x4<amdgpu_synid908_type_dev>`,     :ref:`src1<amdgpu_synid908_src32_2>`::ref:`i8x4<amdgpu_synid908_type_dev>`,     :ref:`src2<amdgpu_synid908_src32_2>`::ref:`i32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot4_u32_u8          :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`u8x4<amdgpu_synid908_type_dev>`,     :ref:`src1<amdgpu_synid908_src32_2>`::ref:`u8x4<amdgpu_synid908_type_dev>`,     :ref:`src2<amdgpu_synid908_src32_2>`::ref:`u32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
     v_dot8_i32_i4          :ref:`vdst<amdgpu_synid908_vdst32_0>`,        :ref:`src0<amdgpu_synid908_src32_1>`::ref:`i4x8<amdgpu_synid908_type_dev>`,     :ref:`src1<amdgpu_synid908_src32_2>`::ref:`i4x8<amdgpu_synid908_type_dev>`,     :ref:`src2<amdgpu_synid908_src32_2>`::ref:`i32<amdgpu_synid908_type_dev>`       :ref:`clamp<amdgpu_synid_clamp>`
@@ -150,6 +150,8 @@ VOP3P
     gfx908_src32_1
     gfx908_src32_2
     gfx908_src32_3
+    gfx908_src32_4
+    gfx908_src32_5
     gfx908_vaddr_flat_global
     gfx908_vasrc32_0
     gfx908_vasrc64_0
diff --git a/llvm/docs/AMDGPU/gfx1011_src32_2.rst b/llvm/docs/AMDGPU/gfx1011_src32_2.rst
new file mode 100644
index 000000000000..6c62701709a1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1011_src32_2.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid1011_src32_2:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx1011_src32_3.rst b/llvm/docs/AMDGPU/gfx1011_src32_3.rst
new file mode 100644
index 000000000000..00ffe2317566
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1011_src32_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid1011_src32_3:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_addr_mimg.rst b/llvm/docs/AMDGPU/gfx10_addr_mimg.rst
index 882fd8c9f61a..7555e2836ee0 100644
--- a/llvm/docs/AMDGPU/gfx10_addr_mimg.rst
+++ b/llvm/docs/AMDGPU/gfx10_addr_mimg.rst
@@ -17,7 +17,7 @@ This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_syn
 *Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
 
 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
-* If specified using :ref:`standard VGPR syntax<amdgpu_synid_vcc_lo>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
+* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1, 2, 3, 4, 8 or 16 dwords. Note that assembler currently supports a limited range of register sequences.
 
 
 *Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_attr.rst b/llvm/docs/AMDGPU/gfx10_attr.rst
index f32f085f35ba..c3091bbad7af 100644
--- a/llvm/docs/AMDGPU/gfx10_attr.rst
+++ b/llvm/docs/AMDGPU/gfx10_attr.rst
@@ -27,4 +27,3 @@ Examples:
 
     v_interp_p1_f32 v1, v0, attr0.x
     v_interp_p1_f32 v1, v0, attr32.w
-
diff --git a/llvm/docs/AMDGPU/gfx10_bimm16.rst b/llvm/docs/AMDGPU/gfx10_bimm16.rst
index 689ac46d94ba..b871ef27f96c 100644
--- a/llvm/docs/AMDGPU/gfx10_bimm16.rst
+++ b/llvm/docs/AMDGPU/gfx10_bimm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx10_bimm32.rst b/llvm/docs/AMDGPU/gfx10_bimm32.rst
index 7e1bd334ebfc..ebcc691ee258 100644
--- a/llvm/docs/AMDGPU/gfx10_bimm32.rst
+++ b/llvm/docs/AMDGPU/gfx10_bimm32.rst
@@ -11,4 +11,3 @@ imm32
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
-
diff --git a/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst b/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst
index a8d52492f9f0..4cd5a05b41a5 100644
--- a/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst
+++ b/llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst
@@ -18,4 +18,4 @@ Optionally may serve as an output data:
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_fimm16.rst b/llvm/docs/AMDGPU/gfx10_fimm16.rst
index 5c1dccc46892..9ac39c617908 100644
--- a/llvm/docs/AMDGPU/gfx10_fimm16.rst
+++ b/llvm/docs/AMDGPU/gfx10_fimm16.rst
@@ -12,4 +12,3 @@ imm32
 
 A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
 The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.
-
diff --git a/llvm/docs/AMDGPU/gfx10_fimm32.rst b/llvm/docs/AMDGPU/gfx10_fimm32.rst
index 258762c4ed7e..7b181912e38f 100644
--- a/llvm/docs/AMDGPU/gfx10_fimm32.rst
+++ b/llvm/docs/AMDGPU/gfx10_fimm32.rst
@@ -12,4 +12,3 @@ imm32
 
 A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
 The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
-
diff --git a/llvm/docs/AMDGPU/gfx10_hwreg.rst b/llvm/docs/AMDGPU/gfx10_hwreg.rst
index 56e2c66cbcf2..5a114aede062 100644
--- a/llvm/docs/AMDGPU/gfx10_hwreg.rst
+++ b/llvm/docs/AMDGPU/gfx10_hwreg.rst
@@ -79,4 +79,3 @@ Examples:
     s_getreg_b32 s2, hwreg(15)
     s_getreg_b32 s2, hwreg(51, 1, 31)
     s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
-
diff --git a/llvm/docs/AMDGPU/gfx10_label.rst b/llvm/docs/AMDGPU/gfx10_label.rst
index 40c973eaf675..cf1a8ea598f9 100644
--- a/llvm/docs/AMDGPU/gfx10_label.rst
+++ b/llvm/docs/AMDGPU/gfx10_label.rst
@@ -34,4 +34,3 @@ Examples:
 
   label_3 = label_2 + 4
   label_4:
-
diff --git a/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst
index bbf04e7ba5e5..6bffb83d6471 100644
--- a/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx10_mad_type_dev.rst
@@ -14,4 +14,3 @@ This is an *f32* or *f16* operand depending on instruction modifiers:
 
 * Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
 * Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
-
diff --git a/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst
index dfa8c07293fd..05bcc0330840 100644
--- a/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst
index b7e0e3e0f927..15671007c102 100644
--- a/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst
+++ b/llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
-
diff --git a/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst
index 9f6b6abdcb36..50c29b66594d 100644
--- a/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx10_opt.rst b/llvm/docs/AMDGPU/gfx10_opt.rst
index d7dbba331801..16acc93a0414 100644
--- a/llvm/docs/AMDGPU/gfx10_opt.rst
+++ b/llvm/docs/AMDGPU/gfx10_opt.rst
@@ -11,4 +11,3 @@ opt
 ===========================
 
 This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
-
diff --git a/llvm/docs/AMDGPU/gfx10_param.rst b/llvm/docs/AMDGPU/gfx10_param.rst
index afa91e345701..0e59db7e3edf 100644
--- a/llvm/docs/AMDGPU/gfx10_param.rst
+++ b/llvm/docs/AMDGPU/gfx10_param.rst
@@ -19,4 +19,3 @@ Interpolation parameter to read:
     p10          Parameter *P10*.
     p20          Parameter *P20*.
     ============ ===================================
-
diff --git a/llvm/docs/AMDGPU/gfx10_perm_smem.rst b/llvm/docs/AMDGPU/gfx10_perm_smem.rst
index bc12d1566517..d6b3d07024d5 100644
--- a/llvm/docs/AMDGPU/gfx10_perm_smem.rst
+++ b/llvm/docs/AMDGPU/gfx10_perm_smem.rst
@@ -22,4 +22,3 @@ The value is truncated to 7 bits, but only 3 low bits are significant.
     1            Request *write* permission.
     2            Request *execute* permission.
     ============ ==============================
-
diff --git a/llvm/docs/AMDGPU/gfx10_ret.rst b/llvm/docs/AMDGPU/gfx10_ret.rst
index 2003437c2079..0809f6ca913c 100644
--- a/llvm/docs/AMDGPU/gfx10_ret.rst
+++ b/llvm/docs/AMDGPU/gfx10_ret.rst
@@ -11,4 +11,3 @@ dst
 ===========================
 
 This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
-
diff --git a/llvm/docs/AMDGPU/gfx10_sdata64_0.rst b/llvm/docs/AMDGPU/gfx10_sdata64_0.rst
index a47fb083a834..f03938a3c8aa 100644
--- a/llvm/docs/AMDGPU/gfx10_sdata64_0.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdata64_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst64_0.rst b/llvm/docs/AMDGPU/gfx10_sdst64_0.rst
index a70da808e0d8..75797f2a4332 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst64_0.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst64_0.rst
@@ -14,4 +14,4 @@ Instruction output.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_sdst64_1.rst b/llvm/docs/AMDGPU/gfx10_sdst64_1.rst
index 483a4e3f1a79..be8b6a06cec1 100644
--- a/llvm/docs/AMDGPU/gfx10_sdst64_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_sdst64_1.rst
@@ -14,4 +14,4 @@ Instruction output.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`exec<amdgpu_synid_exec>`
diff --git a/llvm/docs/AMDGPU/gfx10_simm16.rst b/llvm/docs/AMDGPU/gfx10_simm16.rst
index 365600a5b2e3..e88003ffaf05 100644
--- a/llvm/docs/AMDGPU/gfx10_simm16.rst
+++ b/llvm/docs/AMDGPU/gfx10_simm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx10_src32_1.rst b/llvm/docs/AMDGPU/gfx10_src32_1.rst
index a1be1e1c3396..f786f406695d 100644
--- a/llvm/docs/AMDGPU/gfx10_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_src32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_2.rst b/llvm/docs/AMDGPU/gfx10_src32_2.rst
index 9b8fd6f5054b..bb976167ef58 100644
--- a/llvm/docs/AMDGPU/gfx10_src32_2.rst
+++ b/llvm/docs/AMDGPU/gfx10_src32_2.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_3.rst b/llvm/docs/AMDGPU/gfx10_src32_3.rst
index b9348220136d..43bb76b5ac8d 100644
--- a/llvm/docs/AMDGPU/gfx10_src32_3.rst
+++ b/llvm/docs/AMDGPU/gfx10_src32_3.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_4.rst b/llvm/docs/AMDGPU/gfx10_src32_4.rst
new file mode 100644
index 000000000000..127990f08be1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_src32_4:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_5.rst b/llvm/docs/AMDGPU/gfx10_src32_5.rst
new file mode 100644
index 000000000000..b856aa975fa1
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_5.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_src32_5:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_src32_6.rst b/llvm/docs/AMDGPU/gfx10_src32_6.rst
new file mode 100644
index 000000000000..3db381aa1f40
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx10_src32_6.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid10_src32_6:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst b/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst
index 774682627a7a..7e351f44a4ca 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc64_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst b/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst
index bd13d35b2848..45116b00c187 100644
--- a/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst
+++ b/llvm/docs/AMDGPU/gfx10_ssrc64_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`null<amdgpu_synid_null>`
diff --git a/llvm/docs/AMDGPU/gfx10_tgt.rst b/llvm/docs/AMDGPU/gfx10_tgt.rst
index b6569c73b9eb..f562c72962dd 100644
--- a/llvm/docs/AMDGPU/gfx10_tgt.rst
+++ b/llvm/docs/AMDGPU/gfx10_tgt.rst
@@ -22,4 +22,3 @@ An export target:
     prim           Copy primitive (connectivity) data.
     null           Copy nothing.
     ============== ===================================
-
diff --git a/llvm/docs/AMDGPU/gfx10_type_dev.rst b/llvm/docs/AMDGPU/gfx10_type_dev.rst
index 8978fbeb4a0d..dd3d14faaafd 100644
--- a/llvm/docs/AMDGPU/gfx10_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx10_type_dev.rst
@@ -11,4 +11,3 @@ Type deviation
 ===========================
 
 *Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
-
diff --git a/llvm/docs/AMDGPU/gfx10_uimm16.rst b/llvm/docs/AMDGPU/gfx10_uimm16.rst
index 8ade8dd60dae..2814a4b836df 100644
--- a/llvm/docs/AMDGPU/gfx10_uimm16.rst
+++ b/llvm/docs/AMDGPU/gfx10_uimm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst b/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst
index 0d44a1a0caa8..06713f931960 100644
--- a/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst
+++ b/llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst
@@ -15,8 +15,6 @@ A 64-bit flat global address or a 32-bit offset depending on addressing mode:
 * Address = :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid10_saddr_flat_global>` set to :ref:`off<amdgpu_synid_off>`.
 * Address = :ref:`saddr<amdgpu_synid10_saddr_flat_global>` + :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` + :ref:`offset12s<amdgpu_synid_flat_offset12s>`. :ref:`vaddr<amdgpu_synid10_vaddr_flat_global>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid10_saddr_flat_global>` is not :ref:`off<amdgpu_synid_off>`.
 
-.. WARNING:: Assembler currently expects a 64-bit *vaddr* regardless of addressing mode. This have to be fixed.
-
 *Size:* 1 or 2 dwords.
 
 *Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx10_vcc_32.rst b/llvm/docs/AMDGPU/gfx10_vcc_32.rst
index 1e730073c2f0..1525dab0fd5d 100644
--- a/llvm/docs/AMDGPU/gfx10_vcc_32.rst
+++ b/llvm/docs/AMDGPU/gfx10_vcc_32.rst
@@ -14,4 +14,3 @@ Vector condition code. This operand depends on wavefront size:
 
 * Should be :ref:`vcc_lo<amdgpu_synid_vcc_lo>` if wavefront size is 32.
 * Should be :ref:`vcc<amdgpu_synid_vcc>` if wavefront size is 64.
-
diff --git a/llvm/docs/AMDGPU/gfx10_waitcnt.rst b/llvm/docs/AMDGPU/gfx10_waitcnt.rst
index c861fb0113c9..1a7126400dd5 100644
--- a/llvm/docs/AMDGPU/gfx10_waitcnt.rst
+++ b/llvm/docs/AMDGPU/gfx10_waitcnt.rst
@@ -62,4 +62,3 @@ Examples:
     s_waitcnt expcnt(2) lgkmcnt(3)
     s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
     s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
-
diff --git a/llvm/docs/AMDGPU/gfx7_attr.rst b/llvm/docs/AMDGPU/gfx7_attr.rst
index 219b77414ab1..2257f4e1f320 100644
--- a/llvm/docs/AMDGPU/gfx7_attr.rst
+++ b/llvm/docs/AMDGPU/gfx7_attr.rst
@@ -27,4 +27,3 @@ Examples:
 
     v_interp_p1_f32 v1, v0, attr0.x
     v_interp_p1_f32 v1, v0, attr32.w
-
diff --git a/llvm/docs/AMDGPU/gfx7_bimm16.rst b/llvm/docs/AMDGPU/gfx7_bimm16.rst
index 5f1fbc1dcd6c..9b0fb57db376 100644
--- a/llvm/docs/AMDGPU/gfx7_bimm16.rst
+++ b/llvm/docs/AMDGPU/gfx7_bimm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx7_bimm32.rst b/llvm/docs/AMDGPU/gfx7_bimm32.rst
index 45d35ff7adeb..c4ffef8bcdec 100644
--- a/llvm/docs/AMDGPU/gfx7_bimm32.rst
+++ b/llvm/docs/AMDGPU/gfx7_bimm32.rst
@@ -11,4 +11,3 @@ imm32
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
-
diff --git a/llvm/docs/AMDGPU/gfx7_dst_buf_32.rst b/llvm/docs/AMDGPU/gfx7_dst_buf_32.rst
new file mode 100644
index 000000000000..101941195d5d
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx7_dst_buf_32.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid7_dst_buf_32:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx7_fimm32.rst b/llvm/docs/AMDGPU/gfx7_fimm32.rst
index de261aea8dbf..b086074604c6 100644
--- a/llvm/docs/AMDGPU/gfx7_fimm32.rst
+++ b/llvm/docs/AMDGPU/gfx7_fimm32.rst
@@ -12,4 +12,3 @@ imm32
 
 A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
 The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
-
diff --git a/llvm/docs/AMDGPU/gfx7_hwreg.rst b/llvm/docs/AMDGPU/gfx7_hwreg.rst
index b303b6ce8f97..6f7d71e519df 100644
--- a/llvm/docs/AMDGPU/gfx7_hwreg.rst
+++ b/llvm/docs/AMDGPU/gfx7_hwreg.rst
@@ -70,4 +70,3 @@ Examples:
     s_getreg_b32 s2, hwreg(15)
     s_getreg_b32 s2, hwreg(51, 1, 31)
     s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
-
diff --git a/llvm/docs/AMDGPU/gfx7_label.rst b/llvm/docs/AMDGPU/gfx7_label.rst
index 2f6bd68ddc33..6c1a685c3ea9 100644
--- a/llvm/docs/AMDGPU/gfx7_label.rst
+++ b/llvm/docs/AMDGPU/gfx7_label.rst
@@ -34,4 +34,3 @@ Examples:
 
   label_3 = label_2 + 4
   label_4:
-
diff --git a/llvm/docs/AMDGPU/gfx7_mod.rst b/llvm/docs/AMDGPU/gfx7_mod.rst
index fcaa6caf9247..0b03299b254b 100644
--- a/llvm/docs/AMDGPU/gfx7_mod.rst
+++ b/llvm/docs/AMDGPU/gfx7_mod.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx7_opt.rst b/llvm/docs/AMDGPU/gfx7_opt.rst
index 1a48733dda97..d7e59463464b 100644
--- a/llvm/docs/AMDGPU/gfx7_opt.rst
+++ b/llvm/docs/AMDGPU/gfx7_opt.rst
@@ -11,4 +11,3 @@ opt
 ===========================
 
 This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
-
diff --git a/llvm/docs/AMDGPU/gfx7_param.rst b/llvm/docs/AMDGPU/gfx7_param.rst
index 13e533b3b288..e3f9dd23a93a 100644
--- a/llvm/docs/AMDGPU/gfx7_param.rst
+++ b/llvm/docs/AMDGPU/gfx7_param.rst
@@ -19,4 +19,3 @@ Interpolation parameter to read:
     p10          Parameter *P10*.
     p20          Parameter *P20*.
     ============ ===================================
-
diff --git a/llvm/docs/AMDGPU/gfx7_ret.rst b/llvm/docs/AMDGPU/gfx7_ret.rst
index 25301c2cde8f..899a200c38f6 100644
--- a/llvm/docs/AMDGPU/gfx7_ret.rst
+++ b/llvm/docs/AMDGPU/gfx7_ret.rst
@@ -11,4 +11,3 @@ dst
 ===========================
 
 This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
-
diff --git a/llvm/docs/AMDGPU/gfx7_simm16.rst b/llvm/docs/AMDGPU/gfx7_simm16.rst
index 3e5d3700863f..d6890d429c11 100644
--- a/llvm/docs/AMDGPU/gfx7_simm16.rst
+++ b/llvm/docs/AMDGPU/gfx7_simm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx7_tgt.rst b/llvm/docs/AMDGPU/gfx7_tgt.rst
index c407c0c56bbe..8413ad1a6f3e 100644
--- a/llvm/docs/AMDGPU/gfx7_tgt.rst
+++ b/llvm/docs/AMDGPU/gfx7_tgt.rst
@@ -21,4 +21,3 @@ An export target:
     mrtz           Copy pixel depth (Z) data.
     null           Copy nothing.
     ============== ===================================
-
diff --git a/llvm/docs/AMDGPU/gfx7_type_dev.rst b/llvm/docs/AMDGPU/gfx7_type_dev.rst
index 6eab0e1b3964..faef5f4ee3ac 100644
--- a/llvm/docs/AMDGPU/gfx7_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx7_type_dev.rst
@@ -11,4 +11,3 @@ Type deviation
 ===========================
 
 *Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
-
diff --git a/llvm/docs/AMDGPU/gfx7_uimm16.rst b/llvm/docs/AMDGPU/gfx7_uimm16.rst
index d8a1a20528ae..a49ddeb554c2 100644
--- a/llvm/docs/AMDGPU/gfx7_uimm16.rst
+++ b/llvm/docs/AMDGPU/gfx7_uimm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx7_waitcnt.rst b/llvm/docs/AMDGPU/gfx7_waitcnt.rst
index 9566e6c67327..b70c8c32deb3 100644
--- a/llvm/docs/AMDGPU/gfx7_waitcnt.rst
+++ b/llvm/docs/AMDGPU/gfx7_waitcnt.rst
@@ -62,4 +62,3 @@ Examples:
     s_waitcnt expcnt(2) lgkmcnt(3)
     s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
     s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
-
diff --git a/llvm/docs/AMDGPU/gfx8_attr.rst b/llvm/docs/AMDGPU/gfx8_attr.rst
index 12fa2cde8422..eec2a2de4b3b 100644
--- a/llvm/docs/AMDGPU/gfx8_attr.rst
+++ b/llvm/docs/AMDGPU/gfx8_attr.rst
@@ -27,4 +27,3 @@ Examples:
 
     v_interp_p1_f32 v1, v0, attr0.x
     v_interp_p1_f32 v1, v0, attr32.w
-
diff --git a/llvm/docs/AMDGPU/gfx8_bimm16.rst b/llvm/docs/AMDGPU/gfx8_bimm16.rst
index 66875c6024f4..83cac003e488 100644
--- a/llvm/docs/AMDGPU/gfx8_bimm16.rst
+++ b/llvm/docs/AMDGPU/gfx8_bimm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx8_bimm32.rst b/llvm/docs/AMDGPU/gfx8_bimm32.rst
index e46bc3c7ac81..ab5c53a6540a 100644
--- a/llvm/docs/AMDGPU/gfx8_bimm32.rst
+++ b/llvm/docs/AMDGPU/gfx8_bimm32.rst
@@ -11,4 +11,3 @@ imm32
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
-
diff --git a/llvm/docs/AMDGPU/gfx8_dst_buf_32.rst b/llvm/docs/AMDGPU/gfx8_dst_buf_32.rst
new file mode 100644
index 000000000000..e747530d9956
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_dst_buf_32.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_dst_buf_32:
+
+vdst
+===========================
+
+Instruction output: data read from a memory buffer.
+
+*Size:* 1 dword by default. :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx8_fimm16.rst b/llvm/docs/AMDGPU/gfx8_fimm16.rst
index 7abd5987bcdd..2050af2e2874 100644
--- a/llvm/docs/AMDGPU/gfx8_fimm16.rst
+++ b/llvm/docs/AMDGPU/gfx8_fimm16.rst
@@ -12,4 +12,3 @@ imm32
 
 A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
 The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.
-
diff --git a/llvm/docs/AMDGPU/gfx8_fimm32.rst b/llvm/docs/AMDGPU/gfx8_fimm32.rst
index a1556557f1da..49796b47ed08 100644
--- a/llvm/docs/AMDGPU/gfx8_fimm32.rst
+++ b/llvm/docs/AMDGPU/gfx8_fimm32.rst
@@ -12,4 +12,3 @@ imm32
 
 A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
 The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
-
diff --git a/llvm/docs/AMDGPU/gfx8_hwreg.rst b/llvm/docs/AMDGPU/gfx8_hwreg.rst
index 87d788849110..36e5c588a238 100644
--- a/llvm/docs/AMDGPU/gfx8_hwreg.rst
+++ b/llvm/docs/AMDGPU/gfx8_hwreg.rst
@@ -70,4 +70,3 @@ Examples:
     s_getreg_b32 s2, hwreg(15)
     s_getreg_b32 s2, hwreg(51, 1, 31)
     s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
-
diff --git a/llvm/docs/AMDGPU/gfx8_imask.rst b/llvm/docs/AMDGPU/gfx8_imask.rst
index 55e9a244bdcb..1b0a066faca5 100644
--- a/llvm/docs/AMDGPU/gfx8_imask.rst
+++ b/llvm/docs/AMDGPU/gfx8_imask.rst
@@ -63,4 +63,3 @@ Examples:
     s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST)      // the same as above
 
     s_set_gpr_idx_mode gpr_idx(DST,SRC1)
-
diff --git a/llvm/docs/AMDGPU/gfx8_label.rst b/llvm/docs/AMDGPU/gfx8_label.rst
index 4f10c76f2687..d81fe9f0e2a0 100644
--- a/llvm/docs/AMDGPU/gfx8_label.rst
+++ b/llvm/docs/AMDGPU/gfx8_label.rst
@@ -34,4 +34,3 @@ Examples:
 
   label_3 = label_2 + 4
   label_4:
-
diff --git a/llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst
index be7b4b511b17..09790e48bc1b 100644
--- a/llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst
index b48c521f3b39..64141c5104f1 100644
--- a/llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst
+++ b/llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
-
diff --git a/llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst
index 960e8b1f38f1..a3a4c6043833 100644
--- a/llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx8_opt.rst b/llvm/docs/AMDGPU/gfx8_opt.rst
index 417d7fa1ff38..f9352288d073 100644
--- a/llvm/docs/AMDGPU/gfx8_opt.rst
+++ b/llvm/docs/AMDGPU/gfx8_opt.rst
@@ -11,4 +11,3 @@ opt
 ===========================
 
 This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
-
diff --git a/llvm/docs/AMDGPU/gfx8_param.rst b/llvm/docs/AMDGPU/gfx8_param.rst
index 0bd88549f092..90d7eada07d2 100644
--- a/llvm/docs/AMDGPU/gfx8_param.rst
+++ b/llvm/docs/AMDGPU/gfx8_param.rst
@@ -19,4 +19,3 @@ Interpolation parameter to read:
     p10          Parameter *P10*.
     p20          Parameter *P20*.
     ============ ===================================
-
diff --git a/llvm/docs/AMDGPU/gfx8_perm_smem.rst b/llvm/docs/AMDGPU/gfx8_perm_smem.rst
index 75d02ddac796..b18920bd1142 100644
--- a/llvm/docs/AMDGPU/gfx8_perm_smem.rst
+++ b/llvm/docs/AMDGPU/gfx8_perm_smem.rst
@@ -22,4 +22,3 @@ The value is truncated to 7 bits, but only 3 low bits are significant.
     1            Request *write* permission.
     2            Request *execute* permission.
     ============ ==============================
-
diff --git a/llvm/docs/AMDGPU/gfx8_ret.rst b/llvm/docs/AMDGPU/gfx8_ret.rst
index 91fdaf378a1d..b4b89d8e6477 100644
--- a/llvm/docs/AMDGPU/gfx8_ret.rst
+++ b/llvm/docs/AMDGPU/gfx8_ret.rst
@@ -11,4 +11,3 @@ dst
 ===========================
 
 This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
-
diff --git a/llvm/docs/AMDGPU/gfx8_simm16.rst b/llvm/docs/AMDGPU/gfx8_simm16.rst
index 86161c5400ef..4155272ebfe8 100644
--- a/llvm/docs/AMDGPU/gfx8_simm16.rst
+++ b/llvm/docs/AMDGPU/gfx8_simm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx8_src32_1.rst b/llvm/docs/AMDGPU/gfx8_src32_1.rst
index ea64ab1a9225..bd06181f7d3e 100644
--- a/llvm/docs/AMDGPU/gfx8_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx8_src32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_2.rst b/llvm/docs/AMDGPU/gfx8_src32_2.rst
index 016e7b9b5285..3d8c63b19e3a 100644
--- a/llvm/docs/AMDGPU/gfx8_src32_2.rst
+++ b/llvm/docs/AMDGPU/gfx8_src32_2.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_3.rst b/llvm/docs/AMDGPU/gfx8_src32_3.rst
index ea3164d08b08..19071fa8fde2 100644
--- a/llvm/docs/AMDGPU/gfx8_src32_3.rst
+++ b/llvm/docs/AMDGPU/gfx8_src32_3.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_4.rst b/llvm/docs/AMDGPU/gfx8_src32_4.rst
new file mode 100644
index 000000000000..0b71eec0f2c3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_src32_4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src32_4:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_5.rst b/llvm/docs/AMDGPU/gfx8_src32_5.rst
new file mode 100644
index 000000000000..f37bd89321da
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_src32_5.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src32_5:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_6.rst b/llvm/docs/AMDGPU/gfx8_src32_6.rst
new file mode 100644
index 000000000000..2fe88a33a463
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_src32_6.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src32_6:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx8_src32_7.rst b/llvm/docs/AMDGPU/gfx8_src32_7.rst
new file mode 100644
index 000000000000..c6b2cacd0b26
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx8_src32_7.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid8_src32_7:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`trap<amdgpu_synid_trap>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx8_tgt.rst b/llvm/docs/AMDGPU/gfx8_tgt.rst
index 1be54a73269b..3949028470ac 100644
--- a/llvm/docs/AMDGPU/gfx8_tgt.rst
+++ b/llvm/docs/AMDGPU/gfx8_tgt.rst
@@ -21,4 +21,3 @@ An export target:
     mrtz           Copy pixel depth (Z) data.
     null           Copy nothing.
     ============== ===================================
-
diff --git a/llvm/docs/AMDGPU/gfx8_type_dev.rst b/llvm/docs/AMDGPU/gfx8_type_dev.rst
index 2f5b36f9f9b4..cf8f7f7f00e3 100644
--- a/llvm/docs/AMDGPU/gfx8_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx8_type_dev.rst
@@ -11,4 +11,3 @@ Type deviation
 ===========================
 
 *Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
-
diff --git a/llvm/docs/AMDGPU/gfx8_uimm16.rst b/llvm/docs/AMDGPU/gfx8_uimm16.rst
index 9da1c60a8a73..591d01503120 100644
--- a/llvm/docs/AMDGPU/gfx8_uimm16.rst
+++ b/llvm/docs/AMDGPU/gfx8_uimm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx8_waitcnt.rst b/llvm/docs/AMDGPU/gfx8_waitcnt.rst
index 29b430e07419..70c49d4c5280 100644
--- a/llvm/docs/AMDGPU/gfx8_waitcnt.rst
+++ b/llvm/docs/AMDGPU/gfx8_waitcnt.rst
@@ -62,4 +62,3 @@ Examples:
     s_waitcnt expcnt(2) lgkmcnt(3)
     s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
     s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
-
diff --git a/llvm/docs/AMDGPU/gfx900_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx900_mad_type_dev.rst
index 50c403ef582d..45f5dab2159c 100644
--- a/llvm/docs/AMDGPU/gfx900_mad_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx900_mad_type_dev.rst
@@ -14,4 +14,3 @@ This is an *f32* or *f16* operand depending on instruction modifiers:
 
 * Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
 * Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
-
diff --git a/llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst
index fa0311a9aadf..b5ccdfbd8a63 100644
--- a/llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx900_src32_0.rst b/llvm/docs/AMDGPU/gfx900_src32_0.rst
index 9e2e607a0565..9d7c573e78eb 100644
--- a/llvm/docs/AMDGPU/gfx900_src32_0.rst
+++ b/llvm/docs/AMDGPU/gfx900_src32_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx900_src32_1.rst b/llvm/docs/AMDGPU/gfx900_src32_1.rst
index 82dd50b998d6..a5c23c635c4b 100644
--- a/llvm/docs/AMDGPU/gfx900_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx900_src32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx904_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx904_mad_type_dev.rst
index 6fc3c310880d..13cd62a29470 100644
--- a/llvm/docs/AMDGPU/gfx904_mad_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx904_mad_type_dev.rst
@@ -14,4 +14,3 @@ This is an *f32* or *f16* operand depending on instruction modifiers:
 
 * Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
 * Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
-
diff --git a/llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst
index 814bccdf3a47..f95424960425 100644
--- a/llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx904_src32_0.rst b/llvm/docs/AMDGPU/gfx904_src32_0.rst
index a2930d4c4f90..dbc5ee387393 100644
--- a/llvm/docs/AMDGPU/gfx904_src32_0.rst
+++ b/llvm/docs/AMDGPU/gfx904_src32_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx904_src32_1.rst b/llvm/docs/AMDGPU/gfx904_src32_1.rst
index 23127c6c99b8..38dcc4fc1268 100644
--- a/llvm/docs/AMDGPU/gfx904_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx904_src32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx906_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx906_mad_type_dev.rst
index eb048b0d2d1f..5b5d4b7c2829 100644
--- a/llvm/docs/AMDGPU/gfx906_mad_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx906_mad_type_dev.rst
@@ -14,4 +14,3 @@ This is an *f32* or *f16* operand depending on instruction modifiers:
 
 * Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
 * Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
-
diff --git a/llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst
index 88fdc6f6490e..3ddc6fda098d 100644
--- a/llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst
index 411251baeb27..dbb95496c104 100644
--- a/llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst
+++ b/llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
-
diff --git a/llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst
index ffd6429640d1..1c1e498eb806 100644
--- a/llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx906_src32_0.rst b/llvm/docs/AMDGPU/gfx906_src32_0.rst
index f547beaec23b..d755bd98e1a8 100644
--- a/llvm/docs/AMDGPU/gfx906_src32_0.rst
+++ b/llvm/docs/AMDGPU/gfx906_src32_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx906_src32_1.rst b/llvm/docs/AMDGPU/gfx906_src32_1.rst
index 1fc90e163b1d..8176522793eb 100644
--- a/llvm/docs/AMDGPU/gfx906_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx906_src32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx906_src32_2.rst b/llvm/docs/AMDGPU/gfx906_src32_2.rst
index 6c3bb387c4ed..92e91c5b5416 100644
--- a/llvm/docs/AMDGPU/gfx906_src32_2.rst
+++ b/llvm/docs/AMDGPU/gfx906_src32_2.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx906_src32_3.rst b/llvm/docs/AMDGPU/gfx906_src32_3.rst
new file mode 100644
index 000000000000..98fa3dc575bc
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx906_src32_3.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid906_src32_3:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx906_src32_4.rst b/llvm/docs/AMDGPU/gfx906_src32_4.rst
new file mode 100644
index 000000000000..624f9dff211a
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx906_src32_4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid906_src32_4:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx906_type_dev.rst b/llvm/docs/AMDGPU/gfx906_type_dev.rst
index 02f8d98a3dc4..624d96c8beef 100644
--- a/llvm/docs/AMDGPU/gfx906_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx906_type_dev.rst
@@ -11,4 +11,3 @@ Type deviation
 ===========================
 
 *Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
-
diff --git a/llvm/docs/AMDGPU/gfx908_mad_type_dev.rst b/llvm/docs/AMDGPU/gfx908_mad_type_dev.rst
index bbc3ea9dde55..e86e6d058cb5 100644
--- a/llvm/docs/AMDGPU/gfx908_mad_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx908_mad_type_dev.rst
@@ -14,4 +14,3 @@ This is an *f32* or *f16* operand depending on instruction modifiers:
 
 * Operand size is controlled by :ref:`m_op_sel_hi<amdgpu_synid_mad_mix_op_sel_hi>`.
 * Location of 16-bit operand is controlled by :ref:`m_op_sel<amdgpu_synid_mad_mix_op_sel>`.
-
diff --git a/llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst
index 028a209ebe5f..d89f9832eee6 100644
--- a/llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst
index 1afede5e7474..844c7433ac12 100644
--- a/llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst
+++ b/llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
-
diff --git a/llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst
index 07bec0c68711..6bdd76bb6c3b 100644
--- a/llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx908_offset_buf.rst b/llvm/docs/AMDGPU/gfx908_offset_buf.rst
index 6f3d6d2b96c1..7e39ac3bbb91 100644
--- a/llvm/docs/AMDGPU/gfx908_offset_buf.rst
+++ b/llvm/docs/AMDGPU/gfx908_offset_buf.rst
@@ -14,4 +14,4 @@ An unsigned byte offset.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx908_opt.rst b/llvm/docs/AMDGPU/gfx908_opt.rst
index efd5a79c8a7d..950d8c3ab318 100644
--- a/llvm/docs/AMDGPU/gfx908_opt.rst
+++ b/llvm/docs/AMDGPU/gfx908_opt.rst
@@ -11,4 +11,3 @@ opt
 ===========================
 
 This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
-
diff --git a/llvm/docs/AMDGPU/gfx908_ret.rst b/llvm/docs/AMDGPU/gfx908_ret.rst
index dc8a91c5b4ca..20907addb368 100644
--- a/llvm/docs/AMDGPU/gfx908_ret.rst
+++ b/llvm/docs/AMDGPU/gfx908_ret.rst
@@ -11,4 +11,3 @@ dst
 ===========================
 
 This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
-
diff --git a/llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst b/llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst
index fe9864c237af..050d60f249ec 100644
--- a/llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst
+++ b/llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst
@@ -16,4 +16,4 @@ See :ref:`vaddr<amdgpu_synid908_vaddr_flat_global>` for description of available
 
 *Size:* 2 dwords.
 
-*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`off<amdgpu_synid_off>`
+*Operands:* :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`off<amdgpu_synid_off>`
diff --git a/llvm/docs/AMDGPU/gfx908_src32_0.rst b/llvm/docs/AMDGPU/gfx908_src32_0.rst
index a6bf415d402e..9491a6490ca1 100644
--- a/llvm/docs/AMDGPU/gfx908_src32_0.rst
+++ b/llvm/docs/AMDGPU/gfx908_src32_0.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx908_src32_1.rst b/llvm/docs/AMDGPU/gfx908_src32_1.rst
index 275e4d796b96..db717a93ac17 100644
--- a/llvm/docs/AMDGPU/gfx908_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx908_src32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx908_src32_2.rst b/llvm/docs/AMDGPU/gfx908_src32_2.rst
index 21d0f201f262..f375c555a4df 100644
--- a/llvm/docs/AMDGPU/gfx908_src32_2.rst
+++ b/llvm/docs/AMDGPU/gfx908_src32_2.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx908_src32_3.rst b/llvm/docs/AMDGPU/gfx908_src32_3.rst
index 0e9573d45da4..ca445e87ef10 100644
--- a/llvm/docs/AMDGPU/gfx908_src32_3.rst
+++ b/llvm/docs/AMDGPU/gfx908_src32_3.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx908_src32_4.rst b/llvm/docs/AMDGPU/gfx908_src32_4.rst
new file mode 100644
index 000000000000..aab1b9978ac3
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx908_src32_4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid908_src32_4:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx908_src32_5.rst b/llvm/docs/AMDGPU/gfx908_src32_5.rst
new file mode 100644
index 000000000000..220dc443e891
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx908_src32_5.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid908_src32_5:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx908_type_dev.rst b/llvm/docs/AMDGPU/gfx908_type_dev.rst
index 8d8da92eb1cf..1321aae8e260 100644
--- a/llvm/docs/AMDGPU/gfx908_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx908_type_dev.rst
@@ -11,4 +11,3 @@ Type deviation
 ===========================
 
 *Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
-
diff --git a/llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst b/llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst
index 7b53cb3c7226..d7da4774a94e 100644
--- a/llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst
+++ b/llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst
@@ -15,8 +15,6 @@ A 64-bit flat global address or a 32-bit offset depending on addressing mode:
 * Address = :ref:`vaddr<amdgpu_synid908_vaddr_flat_global>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid908_vaddr_flat_global>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid908_saddr_flat_global>` set to :ref:`off<amdgpu_synid_off>`.
 * Address = :ref:`saddr<amdgpu_synid908_saddr_flat_global>` + :ref:`vaddr<amdgpu_synid908_vaddr_flat_global>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid908_vaddr_flat_global>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid908_saddr_flat_global>` is not :ref:`off<amdgpu_synid_off>`.
 
-.. WARNING:: Assembler currently expects a 64-bit *vaddr* regardless of addressing mode. This have to be fixed.
-
 *Size:* 1 or 2 dwords.
 
 *Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_attr.rst b/llvm/docs/AMDGPU/gfx9_attr.rst
index faffcc7ed18a..10d1b120bc09 100644
--- a/llvm/docs/AMDGPU/gfx9_attr.rst
+++ b/llvm/docs/AMDGPU/gfx9_attr.rst
@@ -27,4 +27,3 @@ Examples:
 
     v_interp_p1_f32 v1, v0, attr0.x
     v_interp_p1_f32 v1, v0, attr32.w
-
diff --git a/llvm/docs/AMDGPU/gfx9_bimm16.rst b/llvm/docs/AMDGPU/gfx9_bimm16.rst
index 6e961167f47a..47930426f4fe 100644
--- a/llvm/docs/AMDGPU/gfx9_bimm16.rst
+++ b/llvm/docs/AMDGPU/gfx9_bimm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 A 16-bit :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx9_bimm32.rst b/llvm/docs/AMDGPU/gfx9_bimm32.rst
index 22286f1d2720..4ac0a97e9521 100644
--- a/llvm/docs/AMDGPU/gfx9_bimm32.rst
+++ b/llvm/docs/AMDGPU/gfx9_bimm32.rst
@@ -11,4 +11,3 @@ imm32
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value is truncated to 32 bits.
-
diff --git a/llvm/docs/AMDGPU/gfx9_fimm16.rst b/llvm/docs/AMDGPU/gfx9_fimm16.rst
index 53432d2594a2..75d3b758a680 100644
--- a/llvm/docs/AMDGPU/gfx9_fimm16.rst
+++ b/llvm/docs/AMDGPU/gfx9_fimm16.rst
@@ -12,4 +12,3 @@ imm32
 
 A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
 The value is converted to *f16* as described :ref:`here<amdgpu_synid_fp_conv>`.
-
diff --git a/llvm/docs/AMDGPU/gfx9_fimm32.rst b/llvm/docs/AMDGPU/gfx9_fimm32.rst
index e3198735ae7a..93507aedfb0a 100644
--- a/llvm/docs/AMDGPU/gfx9_fimm32.rst
+++ b/llvm/docs/AMDGPU/gfx9_fimm32.rst
@@ -12,4 +12,3 @@ imm32
 
 A :ref:`floating-point_number<amdgpu_synid_floating-point_number>`, an :ref:`integer_number<amdgpu_synid_integer_number>`, or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`.
 The value is converted to *f32* as described :ref:`here<amdgpu_synid_fp_conv>`.
-
diff --git a/llvm/docs/AMDGPU/gfx9_hwreg.rst b/llvm/docs/AMDGPU/gfx9_hwreg.rst
index b0c70cb6ccf8..04473ec84c76 100644
--- a/llvm/docs/AMDGPU/gfx9_hwreg.rst
+++ b/llvm/docs/AMDGPU/gfx9_hwreg.rst
@@ -71,4 +71,3 @@ Examples:
     s_getreg_b32 s2, hwreg(15)
     s_getreg_b32 s2, hwreg(51, 1, 31)
     s_getreg_b32 s2, hwreg(HW_REG_LDS_ALLOC, 0, 1)
-
diff --git a/llvm/docs/AMDGPU/gfx9_imask.rst b/llvm/docs/AMDGPU/gfx9_imask.rst
index 22d73cb4ec04..c0cc3723069d 100644
--- a/llvm/docs/AMDGPU/gfx9_imask.rst
+++ b/llvm/docs/AMDGPU/gfx9_imask.rst
@@ -63,4 +63,3 @@ Examples:
     s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST)      // the same as above
 
     s_set_gpr_idx_mode gpr_idx(DST,SRC1)
-
diff --git a/llvm/docs/AMDGPU/gfx9_label.rst b/llvm/docs/AMDGPU/gfx9_label.rst
index 7348fc914887..1f4c8465bab7 100644
--- a/llvm/docs/AMDGPU/gfx9_label.rst
+++ b/llvm/docs/AMDGPU/gfx9_label.rst
@@ -34,4 +34,3 @@ Examples:
 
   label_3 = label_2 + 4
   label_4:
-
diff --git a/llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst b/llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst
index ccbad8a5c87c..b3e9fc2730b9 100644
--- a/llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst b/llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst
index e832097f340e..f0adfa6d4acf 100644
--- a/llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst
+++ b/llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with integer operand modifier :ref:`sext<amdgpu_synid_sext>`.
-
diff --git a/llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst b/llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst
index 2dac4b1bd7d3..c7f33436b351 100644
--- a/llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst
+++ b/llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst
@@ -11,4 +11,3 @@ m
 ===========================
 
 This operand may be used with floating point operand modifiers :ref:`abs<amdgpu_synid_abs>` and :ref:`neg<amdgpu_synid_neg>`.
-
diff --git a/llvm/docs/AMDGPU/gfx9_opt.rst b/llvm/docs/AMDGPU/gfx9_opt.rst
index 50d73f9fcde9..19eefec0b4ec 100644
--- a/llvm/docs/AMDGPU/gfx9_opt.rst
+++ b/llvm/docs/AMDGPU/gfx9_opt.rst
@@ -11,4 +11,3 @@ opt
 ===========================
 
 This is an optional operand. It must be used if and only if :ref:`glc<amdgpu_synid_glc>` is specified.
-
diff --git a/llvm/docs/AMDGPU/gfx9_param.rst b/llvm/docs/AMDGPU/gfx9_param.rst
index 2831a65820f8..234fbc512ed0 100644
--- a/llvm/docs/AMDGPU/gfx9_param.rst
+++ b/llvm/docs/AMDGPU/gfx9_param.rst
@@ -19,4 +19,3 @@ Interpolation parameter to read:
     p10          Parameter *P10*.
     p20          Parameter *P20*.
     ============ ===================================
-
diff --git a/llvm/docs/AMDGPU/gfx9_perm_smem.rst b/llvm/docs/AMDGPU/gfx9_perm_smem.rst
index d13c566789cf..0d24d5f16e46 100644
--- a/llvm/docs/AMDGPU/gfx9_perm_smem.rst
+++ b/llvm/docs/AMDGPU/gfx9_perm_smem.rst
@@ -22,4 +22,3 @@ The value is truncated to 7 bits, but only 3 low bits are significant.
     1            Request *write* permission.
     2            Request *execute* permission.
     ============ ==============================
-
diff --git a/llvm/docs/AMDGPU/gfx9_ret.rst b/llvm/docs/AMDGPU/gfx9_ret.rst
index 7015be6298d7..6f132293bcb3 100644
--- a/llvm/docs/AMDGPU/gfx9_ret.rst
+++ b/llvm/docs/AMDGPU/gfx9_ret.rst
@@ -11,4 +11,3 @@ dst
 ===========================
 
 This is an input operand. It may optionally serve as a destination if :ref:`glc<amdgpu_synid_glc>` is specified.
-
diff --git a/llvm/docs/AMDGPU/gfx9_simm16.rst b/llvm/docs/AMDGPU/gfx9_simm16.rst
index 4f734a04239a..6bc9ba70da0b 100644
--- a/llvm/docs/AMDGPU/gfx9_simm16.rst
+++ b/llvm/docs/AMDGPU/gfx9_simm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range -32768..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx9_src32_1.rst b/llvm/docs/AMDGPU/gfx9_src32_1.rst
index b96594c55041..b65ec271a16a 100644
--- a/llvm/docs/AMDGPU/gfx9_src32_1.rst
+++ b/llvm/docs/AMDGPU/gfx9_src32_1.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_2.rst b/llvm/docs/AMDGPU/gfx9_src32_2.rst
index 045b913a1293..cc306a913c63 100644
--- a/llvm/docs/AMDGPU/gfx9_src32_2.rst
+++ b/llvm/docs/AMDGPU/gfx9_src32_2.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_3.rst b/llvm/docs/AMDGPU/gfx9_src32_3.rst
index 2bb797215c2b..2f13457ea177 100644
--- a/llvm/docs/AMDGPU/gfx9_src32_3.rst
+++ b/llvm/docs/AMDGPU/gfx9_src32_3.rst
@@ -14,4 +14,4 @@ Instruction input.
 
 *Size:* 1 dword.
 
-*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`, :ref:`literal<amdgpu_synid_literal>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_4.rst b/llvm/docs/AMDGPU/gfx9_src32_4.rst
new file mode 100644
index 000000000000..f146fe8065fd
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src32_4.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src32_4:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_5.rst b/llvm/docs/AMDGPU/gfx9_src32_5.rst
new file mode 100644
index 000000000000..4ac258533daf
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src32_5.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src32_5:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`constant<amdgpu_synid_constant>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_6.rst b/llvm/docs/AMDGPU/gfx9_src32_6.rst
new file mode 100644
index 000000000000..42377cba7c23
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src32_6.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src32_6:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`lds_direct<amdgpu_synid_lds_direct>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx9_src32_7.rst b/llvm/docs/AMDGPU/gfx9_src32_7.rst
new file mode 100644
index 000000000000..809cd04b60fe
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx9_src32_7.rst
@@ -0,0 +1,17 @@
+..
+    **************************************************
+    *                                                *
+    *   Automatically generated file, do not edit!   *
+    *                                                *
+    **************************************************
+
+.. _amdgpu_synid9_src32_7:
+
+src
+===========================
+
+Instruction input.
+
+*Size:* 1 dword.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`s<amdgpu_synid_s>`, :ref:`flat_scratch<amdgpu_synid_flat_scratch>`, :ref:`xnack<amdgpu_synid_xnack>`, :ref:`vcc<amdgpu_synid_vcc>`, :ref:`ttmp<amdgpu_synid_ttmp>`, :ref:`m0<amdgpu_synid_m0>`, :ref:`exec<amdgpu_synid_exec>`, :ref:`vccz<amdgpu_synid_vccz>`, :ref:`execz<amdgpu_synid_execz>`, :ref:`scc<amdgpu_synid_scc>`, :ref:`iconst<amdgpu_synid_iconst>`
diff --git a/llvm/docs/AMDGPU/gfx9_tgt.rst b/llvm/docs/AMDGPU/gfx9_tgt.rst
index 3ba8baebb3bc..066a2f3dfb9c 100644
--- a/llvm/docs/AMDGPU/gfx9_tgt.rst
+++ b/llvm/docs/AMDGPU/gfx9_tgt.rst
@@ -21,4 +21,3 @@ An export target:
     mrtz           Copy pixel depth (Z) data.
     null           Copy nothing.
     ============== ===================================
-
diff --git a/llvm/docs/AMDGPU/gfx9_type_dev.rst b/llvm/docs/AMDGPU/gfx9_type_dev.rst
index ae2b0bf6c50c..7dc86096d412 100644
--- a/llvm/docs/AMDGPU/gfx9_type_dev.rst
+++ b/llvm/docs/AMDGPU/gfx9_type_dev.rst
@@ -11,4 +11,3 @@ Type deviation
 ===========================
 
 *Type* of this operand differs from *type* :ref:`implied by the opcode<amdgpu_syn_instruction_type>`. This tag specifies actual operand *type*.
-
diff --git a/llvm/docs/AMDGPU/gfx9_uimm16.rst b/llvm/docs/AMDGPU/gfx9_uimm16.rst
index dd3c9b4a2995..c14915b01211 100644
--- a/llvm/docs/AMDGPU/gfx9_uimm16.rst
+++ b/llvm/docs/AMDGPU/gfx9_uimm16.rst
@@ -11,4 +11,3 @@ imm16
 ===========================
 
 An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..65535.
-
diff --git a/llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst b/llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst
index e08e8fb762d8..0ecd151edbb0 100644
--- a/llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst
+++ b/llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst
@@ -15,8 +15,6 @@ A 64-bit flat global address or a 32-bit offset depending on addressing mode:
 * Address = :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 64-bit address. This mode is indicated by :ref:`saddr<amdgpu_synid9_saddr_flat_global>` set to :ref:`off<amdgpu_synid_off>`.
 * Address = :ref:`saddr<amdgpu_synid9_saddr_flat_global>` + :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` + :ref:`offset13s<amdgpu_synid_flat_offset13s>`. :ref:`vaddr<amdgpu_synid9_vaddr_flat_global>` is a 32-bit offset. This mode is used when :ref:`saddr<amdgpu_synid9_saddr_flat_global>` is not :ref:`off<amdgpu_synid_off>`.
 
-.. WARNING:: Assembler currently expects a 64-bit *vaddr* regardless of addressing mode. This have to be fixed.
-
 *Size:* 1 or 2 dwords.
 
 *Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx9_waitcnt.rst b/llvm/docs/AMDGPU/gfx9_waitcnt.rst
index 342f8c7fdb9e..73c0b6331544 100644
--- a/llvm/docs/AMDGPU/gfx9_waitcnt.rst
+++ b/llvm/docs/AMDGPU/gfx9_waitcnt.rst
@@ -62,4 +62,3 @@ Examples:
     s_waitcnt expcnt(2) lgkmcnt(3)
     s_waitcnt vmcnt(1), expcnt(2), lgkmcnt(3)
     s_waitcnt vmcnt(1) & lgkmcnt_sat(100) & expcnt(2)
-
diff --git a/llvm/docs/AMDGPUInstructionNotation.rst b/llvm/docs/AMDGPUInstructionNotation.rst
index 7f23cf406cfe..c03dd3d12e1d 100644
--- a/llvm/docs/AMDGPUInstructionNotation.rst
+++ b/llvm/docs/AMDGPUInstructionNotation.rst
@@ -10,7 +10,7 @@ AMDGPU Instructions Notation
 Introduction
 ============
 
-This is an overview of notation used to describe the syntax of AMDGPU assembler instructions.
+This is an overview of notation used to describe syntax of AMDGPU assembler instructions.
 
 This notation mimics the :ref:`syntax of assembler instructions<amdgpu_syn_instructions>`
 except that instead of real operands and modifiers it provides references to their description.
diff --git a/llvm/docs/AMDGPUInstructionSyntax.rst b/llvm/docs/AMDGPUInstructionSyntax.rst
index 588635023cbf..04c5180c6acc 100644
--- a/llvm/docs/AMDGPUInstructionSyntax.rst
+++ b/llvm/docs/AMDGPUInstructionSyntax.rst
@@ -78,9 +78,9 @@ The size of data is specified by size suffices:
     xyz               b96                 3
     xyzw              b128                4
     d16_x             b16                 1
-    d16_xy            b16x2               2 for GFX8.0, 1 for GFX8.1 and GFX9
-    d16_xyz           b16x3               3 for GFX8.0, 2 for GFX8.1 and GFX9
-    d16_xyzw          b16x4               4 for GFX8.0, 2 for GFX8.1 and GFX9
+    d16_xy            b16x2               2 for GFX8.0, 1 for GFX8.1 and GFX9+
+    d16_xyz           b16x3               3 for GFX8.0, 2 for GFX8.1 and GFX9+
+    d16_xyzw          b16x4               4 for GFX8.0, 2 for GFX8.1 and GFX9+
     ================= =================== =====================================
 
 .. WARNING::
diff --git a/llvm/docs/AMDGPUModifierSyntax.rst b/llvm/docs/AMDGPUModifierSyntax.rst
index 5e29004b4d6e..214d1bda1cf1 100644
--- a/llvm/docs/AMDGPUModifierSyntax.rst
+++ b/llvm/docs/AMDGPUModifierSyntax.rst
@@ -733,19 +733,212 @@ tfe
 
 See a description :ref:`here<amdgpu_synid_tfe>`.
 
-.. _amdgpu_synid_dfmt:
+.. _amdgpu_synid_fmt:
 
-dfmt
+fmt
+~~~
+
+Specifies data and numeric formats used by the operation.
+The default numeric format is BUF_NUM_FORMAT_UNORM.
+The default data format is BUF_DATA_FORMAT_8.
+
+    ========================================= ===============================================================
+    Syntax                                    Description
+    ========================================= ===============================================================
+    format:{0..127}                           Use format specified as either an
+                                              :ref:`integer number<amdgpu_synid_integer_number>` or an
+                                              :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+    format:[<data format>]                    Use the specified data format and
+                                              default numeric format.
+    format:[<numeric format>]                 Use the specified numeric format and
+                                              default data format.
+    format:[<data format>, <numeric format>]  Use the specified data and numeric formats.
+    format:[<numeric format>, <data format>]  Use the specified data and numeric formats.
+    ========================================= ===============================================================
+
+.. _amdgpu_synid_format_data:
+
+Supported data formats are defined in the following table:
+
+    ========================================= ===============================
+    Syntax                                    Note
+    ========================================= ===============================
+    BUF_DATA_FORMAT_INVALID
+    BUF_DATA_FORMAT_8                         Default value.
+    BUF_DATA_FORMAT_16
+    BUF_DATA_FORMAT_8_8
+    BUF_DATA_FORMAT_32
+    BUF_DATA_FORMAT_16_16
+    BUF_DATA_FORMAT_10_11_11
+    BUF_DATA_FORMAT_11_11_10
+    BUF_DATA_FORMAT_10_10_10_2
+    BUF_DATA_FORMAT_2_10_10_10
+    BUF_DATA_FORMAT_8_8_8_8
+    BUF_DATA_FORMAT_32_32
+    BUF_DATA_FORMAT_16_16_16_16
+    BUF_DATA_FORMAT_32_32_32
+    BUF_DATA_FORMAT_32_32_32_32
+    BUF_DATA_FORMAT_RESERVED_15
+    ========================================= ===============================
+
+.. _amdgpu_synid_format_num:
+
+Supported numeric formats are defined below:
+
+    ========================================= ===============================
+    Syntax                                    Note
+    ========================================= ===============================
+    BUF_NUM_FORMAT_UNORM                      Default value.
+    BUF_NUM_FORMAT_SNORM
+    BUF_NUM_FORMAT_USCALED
+    BUF_NUM_FORMAT_SSCALED
+    BUF_NUM_FORMAT_UINT
+    BUF_NUM_FORMAT_SINT
+    BUF_NUM_FORMAT_SNORM_OGL                  GFX7 only.
+    BUF_NUM_FORMAT_RESERVED_6                 GFX8 and GFX9 only.
+    BUF_NUM_FORMAT_FLOAT
+    ========================================= ===============================
+
+Examples:
+
+.. parsed-literal::
+
+  format:0
+  format:127
+  format:[BUF_DATA_FORMAT_16]
+  format:[BUF_DATA_FORMAT_16,BUF_NUM_FORMAT_SSCALED]
+  format:[BUF_NUM_FORMAT_FLOAT]
+
+.. _amdgpu_synid_ufmt:
+
+ufmt
 ~~~~
 
-TBD
+Specifies a unified format used by the operation.
+The default format is BUF_FMT_8_UNORM.
+GFX10 only.
 
-.. _amdgpu_synid_nfmt:
+    ========================================= ===============================================================
+    Syntax                                    Description
+    ========================================= ===============================================================
+    format:{0..127}                           Use unified format specified as either an
+                                              :ref:`integer number<amdgpu_synid_integer_number>` or an
+                                              :ref:`absolute expression<amdgpu_synid_absolute_expression>`.
+                                              Note that unified format numbers are not compatible with
+                                              format numbers used for pre-GFX10 ISA.
+    format:[<unified format>]                 Use the specified unified format.
+    ========================================= ===============================================================
 
-nfmt
-~~~~
+Unified format is a replacement for :ref:`data<amdgpu_synid_format_data>`
+and :ref:`numeric<amdgpu_synid_format_num>` formats. For compatibility with older ISA,
+:ref:`syntax with data and numeric formats<amdgpu_synid_fmt>` is still accepthed
+provided that the combination of formats can be mapped to a unified format.
 
-TBD
+Supported unified formats and equivalent combinations of data and numeric formats
+are defined below:
+
+    ============================== ============================== =============================
+    Syntax                         Equivalent Data Format         Equivalent Numeric Format
+    ============================== ============================== =============================
+    BUF_FMT_INVALID                BUF_DATA_FORMAT_INVALID        BUF_NUM_FORMAT_UNORM
+
+    BUF_FMT_8_UNORM                BUF_DATA_FORMAT_8              BUF_NUM_FORMAT_UNORM
+    BUF_FMT_8_SNORM                BUF_DATA_FORMAT_8              BUF_NUM_FORMAT_SNORM
+    BUF_FMT_8_USCALED              BUF_DATA_FORMAT_8              BUF_NUM_FORMAT_USCALED
+    BUF_FMT_8_SSCALED              BUF_DATA_FORMAT_8              BUF_NUM_FORMAT_SSCALED
+    BUF_FMT_8_UINT                 BUF_DATA_FORMAT_8              BUF_NUM_FORMAT_UINT
+    BUF_FMT_8_SINT                 BUF_DATA_FORMAT_8              BUF_NUM_FORMAT_SINT
+
+    BUF_FMT_16_UNORM               BUF_DATA_FORMAT_16             BUF_NUM_FORMAT_UNORM
+    BUF_FMT_16_SNORM               BUF_DATA_FORMAT_16             BUF_NUM_FORMAT_SNORM
+    BUF_FMT_16_USCALED             BUF_DATA_FORMAT_16             BUF_NUM_FORMAT_USCALED
+    BUF_FMT_16_SSCALED             BUF_DATA_FORMAT_16             BUF_NUM_FORMAT_SSCALED
+    BUF_FMT_16_UINT                BUF_DATA_FORMAT_16             BUF_NUM_FORMAT_UINT
+    BUF_FMT_16_SINT                BUF_DATA_FORMAT_16             BUF_NUM_FORMAT_SINT
+    BUF_FMT_16_FLOAT               BUF_DATA_FORMAT_16             BUF_NUM_FORMAT_FLOAT
+
+    BUF_FMT_8_8_UNORM              BUF_DATA_FORMAT_8_8            BUF_NUM_FORMAT_UNORM
+    BUF_FMT_8_8_SNORM              BUF_DATA_FORMAT_8_8            BUF_NUM_FORMAT_SNORM
+    BUF_FMT_8_8_USCALED            BUF_DATA_FORMAT_8_8            BUF_NUM_FORMAT_USCALED
+    BUF_FMT_8_8_SSCALED            BUF_DATA_FORMAT_8_8            BUF_NUM_FORMAT_SSCALED
+    BUF_FMT_8_8_UINT               BUF_DATA_FORMAT_8_8            BUF_NUM_FORMAT_UINT
+    BUF_FMT_8_8_SINT               BUF_DATA_FORMAT_8_8            BUF_NUM_FORMAT_SINT
+
+    BUF_FMT_32_UINT                BUF_DATA_FORMAT_32             BUF_NUM_FORMAT_UINT
+    BUF_FMT_32_SINT                BUF_DATA_FORMAT_32             BUF_NUM_FORMAT_SINT
+    BUF_FMT_32_FLOAT               BUF_DATA_FORMAT_32             BUF_NUM_FORMAT_FLOAT
+
+    BUF_FMT_16_16_UNORM            BUF_DATA_FORMAT_16_16          BUF_NUM_FORMAT_UNORM
+    BUF_FMT_16_16_SNORM            BUF_DATA_FORMAT_16_16          BUF_NUM_FORMAT_SNORM
+    BUF_FMT_16_16_USCALED          BUF_DATA_FORMAT_16_16          BUF_NUM_FORMAT_USCALED
+    BUF_FMT_16_16_SSCALED          BUF_DATA_FORMAT_16_16          BUF_NUM_FORMAT_SSCALED
+    BUF_FMT_16_16_UINT             BUF_DATA_FORMAT_16_16          BUF_NUM_FORMAT_UINT
+    BUF_FMT_16_16_SINT             BUF_DATA_FORMAT_16_16          BUF_NUM_FORMAT_SINT
+    BUF_FMT_16_16_FLOAT            BUF_DATA_FORMAT_16_16          BUF_NUM_FORMAT_FLOAT
+
+    BUF_FMT_10_11_11_UNORM         BUF_DATA_FORMAT_10_11_11       BUF_NUM_FORMAT_UNORM
+    BUF_FMT_10_11_11_SNORM         BUF_DATA_FORMAT_10_11_11       BUF_NUM_FORMAT_SNORM
+    BUF_FMT_10_11_11_USCALED       BUF_DATA_FORMAT_10_11_11       BUF_NUM_FORMAT_USCALED
+    BUF_FMT_10_11_11_SSCALED       BUF_DATA_FORMAT_10_11_11       BUF_NUM_FORMAT_SSCALED
+    BUF_FMT_10_11_11_UINT          BUF_DATA_FORMAT_10_11_11       BUF_NUM_FORMAT_UINT
+    BUF_FMT_10_11_11_SINT          BUF_DATA_FORMAT_10_11_11       BUF_NUM_FORMAT_SINT
+    BUF_FMT_10_11_11_FLOAT         BUF_DATA_FORMAT_10_11_11       BUF_NUM_FORMAT_FLOAT
+
+    BUF_FMT_11_11_10_UNORM         BUF_DATA_FORMAT_11_11_10       BUF_NUM_FORMAT_UNORM
+    BUF_FMT_11_11_10_SNORM         BUF_DATA_FORMAT_11_11_10       BUF_NUM_FORMAT_SNORM
+    BUF_FMT_11_11_10_USCALED       BUF_DATA_FORMAT_11_11_10       BUF_NUM_FORMAT_USCALED
+    BUF_FMT_11_11_10_SSCALED       BUF_DATA_FORMAT_11_11_10       BUF_NUM_FORMAT_SSCALED
+    BUF_FMT_11_11_10_UINT          BUF_DATA_FORMAT_11_11_10       BUF_NUM_FORMAT_UINT
+    BUF_FMT_11_11_10_SINT          BUF_DATA_FORMAT_11_11_10       BUF_NUM_FORMAT_SINT
+    BUF_FMT_11_11_10_FLOAT         BUF_DATA_FORMAT_11_11_10       BUF_NUM_FORMAT_FLOAT
+
+    BUF_FMT_10_10_10_2_UNORM       BUF_DATA_FORMAT_10_10_10_2     BUF_NUM_FORMAT_UNORM
+    BUF_FMT_10_10_10_2_SNORM       BUF_DATA_FORMAT_10_10_10_2     BUF_NUM_FORMAT_SNORM
+    BUF_FMT_10_10_10_2_USCALED     BUF_DATA_FORMAT_10_10_10_2     BUF_NUM_FORMAT_USCALED
+    BUF_FMT_10_10_10_2_SSCALED     BUF_DATA_FORMAT_10_10_10_2     BUF_NUM_FORMAT_SSCALED
+    BUF_FMT_10_10_10_2_UINT        BUF_DATA_FORMAT_10_10_10_2     BUF_NUM_FORMAT_UINT
+    BUF_FMT_10_10_10_2_SINT        BUF_DATA_FORMAT_10_10_10_2     BUF_NUM_FORMAT_SINT
+
+    BUF_FMT_2_10_10_10_UNORM       BUF_DATA_FORMAT_2_10_10_10     BUF_NUM_FORMAT_UNORM
+    BUF_FMT_2_10_10_10_SNORM       BUF_DATA_FORMAT_2_10_10_10     BUF_NUM_FORMAT_SNORM
+    BUF_FMT_2_10_10_10_USCALED     BUF_DATA_FORMAT_2_10_10_10     BUF_NUM_FORMAT_USCALED
+    BUF_FMT_2_10_10_10_SSCALED     BUF_DATA_FORMAT_2_10_10_10     BUF_NUM_FORMAT_SSCALED
+    BUF_FMT_2_10_10_10_UINT        BUF_DATA_FORMAT_2_10_10_10     BUF_NUM_FORMAT_UINT
+    BUF_FMT_2_10_10_10_SINT        BUF_DATA_FORMAT_2_10_10_10     BUF_NUM_FORMAT_SINT
+
+    BUF_FMT_8_8_8_8_UNORM          BUF_DATA_FORMAT_8_8_8_8        BUF_NUM_FORMAT_UNORM
+    BUF_FMT_8_8_8_8_SNORM          BUF_DATA_FORMAT_8_8_8_8        BUF_NUM_FORMAT_SNORM
+    BUF_FMT_8_8_8_8_USCALED        BUF_DATA_FORMAT_8_8_8_8        BUF_NUM_FORMAT_USCALED
+    BUF_FMT_8_8_8_8_SSCALED        BUF_DATA_FORMAT_8_8_8_8        BUF_NUM_FORMAT_SSCALED
+    BUF_FMT_8_8_8_8_UINT           BUF_DATA_FORMAT_8_8_8_8        BUF_NUM_FORMAT_UINT
+    BUF_FMT_8_8_8_8_SINT           BUF_DATA_FORMAT_8_8_8_8        BUF_NUM_FORMAT_SINT
+
+    BUF_FMT_32_32_UINT             BUF_DATA_FORMAT_32_32          BUF_NUM_FORMAT_UINT
+    BUF_FMT_32_32_SINT             BUF_DATA_FORMAT_32_32          BUF_NUM_FORMAT_SINT
+    BUF_FMT_32_32_FLOAT            BUF_DATA_FORMAT_32_32          BUF_NUM_FORMAT_FLOAT
+
+    BUF_FMT_16_16_16_16_UNORM      BUF_DATA_FORMAT_16_16_16_16    BUF_NUM_FORMAT_UNORM
+    BUF_FMT_16_16_16_16_SNORM      BUF_DATA_FORMAT_16_16_16_16    BUF_NUM_FORMAT_SNORM
+    BUF_FMT_16_16_16_16_USCALED    BUF_DATA_FORMAT_16_16_16_16    BUF_NUM_FORMAT_USCALED
+    BUF_FMT_16_16_16_16_SSCALED    BUF_DATA_FORMAT_16_16_16_16    BUF_NUM_FORMAT_SSCALED
+    BUF_FMT_16_16_16_16_UINT       BUF_DATA_FORMAT_16_16_16_16    BUF_NUM_FORMAT_UINT
+    BUF_FMT_16_16_16_16_SINT       BUF_DATA_FORMAT_16_16_16_16    BUF_NUM_FORMAT_SINT
+    BUF_FMT_16_16_16_16_FLOAT      BUF_DATA_FORMAT_16_16_16_16    BUF_NUM_FORMAT_FLOAT
+
+    BUF_FMT_32_32_32_UINT          BUF_DATA_FORMAT_32_32_32       BUF_NUM_FORMAT_UINT
+    BUF_FMT_32_32_32_SINT          BUF_DATA_FORMAT_32_32_32       BUF_NUM_FORMAT_SINT
+    BUF_FMT_32_32_32_FLOAT         BUF_DATA_FORMAT_32_32_32       BUF_NUM_FORMAT_FLOAT
+    BUF_FMT_32_32_32_32_UINT       BUF_DATA_FORMAT_32_32_32_32    BUF_NUM_FORMAT_UINT
+    BUF_FMT_32_32_32_32_SINT       BUF_DATA_FORMAT_32_32_32_32    BUF_NUM_FORMAT_SINT
+    BUF_FMT_32_32_32_32_FLOAT      BUF_DATA_FORMAT_32_32_32_32    BUF_NUM_FORMAT_FLOAT
+    ============================== ============================== =============================
+
+Examples:
+
+.. parsed-literal::
+
+  format:0
+  format:[BUF_FMT_32_UINT]
 
 SMRD/SMEM Modifiers
 -------------------
@@ -1491,8 +1684,8 @@ See a description :ref:`here<amdgpu_synid_clamp>`.
 
 .. _amdgpu_synid_mad_mix:
 
-VOP3P V_MAD_MIX Modifiers
--------------------------
+VOP3P MAD_MIX/FMA_MIX Modifiers
+-------------------------------
 
 *v_mad_mix\** and *v_fma_mix\**
 instructions use *op_sel* and *op_sel_hi* modifiers
diff --git a/llvm/docs/AMDGPUOperandSyntax.rst b/llvm/docs/AMDGPUOperandSyntax.rst
index 842f49fbf735..a333924feb88 100644
--- a/llvm/docs/AMDGPUOperandSyntax.rst
+++ b/llvm/docs/AMDGPUOperandSyntax.rst
@@ -85,7 +85,7 @@ GFX10 *Image* instructions may use special *NSA* (Non-Sequential Address) syntax
     Syntax                                Description
     ===================================== =================================================
     **[Vm**, \ **Vn**, ... **Vk**\ **]**  A sequence of 32-bit *vector* registers.
-                                          Each register may be specified using a syntax
+                                          Each register may be specified using syntax
                                           defined :ref:`above<amdgpu_synid_v>`.
 
                                           In contrast with standard syntax, registers
@@ -408,6 +408,10 @@ High and low 32 bits of *flat scratch* address may be accessed as separate regis
     [flat_scratch_hi]         High 32 bits of *flat scratch* address register (an SP3 syntax).
     ========================= =========================================================================
 
+Note that *flat_scratch*, *flat_scratch_lo* and *flat_scratch_hi* are not accessible as assembler
+registers in GFX10, but *flat_scratch* is readable/writable with the help of
+*s_get_reg* and *s_set_reg* instructions.
+
 .. _amdgpu_synid_xnack:
 
 xnack
@@ -439,6 +443,10 @@ High and low 32 bits of *xnack mask* may be accessed as separate registers:
     [xnack_mask_hi]       High 32 bits of *xnack mask* register (an SP3 syntax).
     ===================== ==============================================================
 
+Note that *xnack_mask*, *xnack_mask_lo* and *xnack_mask_hi* are not accessible as assembler
+registers in GFX10, but *xnack_mask* is readable/writable with the help of
+*s_get_reg* and *s_set_reg* instructions.
+
 .. _amdgpu_synid_vcc:
 .. _amdgpu_synid_vcc_lo:
 
@@ -632,6 +640,9 @@ Other floating-point numbers have to be encoded as :ref:`literals<amdgpu_synid_l
     0.15915494309189532   1.0/(2.0*pi).                                         GFX8, GFX9, GFX10
     ===================== ===================================================== ==================
 
+.. WARNING:: Floating-point inline constants cannot be used with *16-bit integer* operands. \
+             Assembler will attempt to encode these values as literals.
+
 .. WARNING:: GFX7 does not support inline constants for *f16* operands.
 
 .. _amdgpu_synid_ival:
@@ -859,7 +870,7 @@ operations produce 64-bit integer results.
 Syntax of Expressions
 ---------------------
 
-The syntax of expressions is shown below::
+Syntax of expressions is shown below::
 
     expr ::= expr binop expr | primaryexpr ;
 
@@ -1065,6 +1076,8 @@ Depending on operand kind, this is performed by either assembler or AMDGPU H/W (
     Expected type  Required FP Type Conversion        Description
     ============== ================ ================= =================================================================
     i16, u16, b16  f16              f16(num)          Convert to f16 and use bits of the result as an integer value.
+                                                      The value has to be encoded as a literal or an error occurs.
+                                                      Note that the value cannot be encoded as an inline constant.
     i32, u32, b32  f32              f32(num)          Convert to f32 and use bits of the result as an integer value.
     i64, u64, b64  \-               \-                Conversion disabled.
     f16            f16              f16(num)          Convert to f16.