forked from OSchip/llvm-project
[Codegen] TargetLowering::prepareUREMEqFold(): `x u% C1 ==/!= C2` with tautological C1 u<= C2 (PR35479)
Summary: This is a preparatory cleanup before i add more of this fold to deal with comparisons with non-zero. In essence, the current lowering is: ``` Name: (X % C1) == 0 -> X * C3 <= C4 Pre: (C1 u>> countTrailingZeros(C1)) * C3 == 1 %zz = and i8 C3, 0 ; trick alive into making C3 avaliable in precondition %o0 = urem i8 %x, C1 %r = icmp eq i8 %o0, 0 => %zz = and i8 C3, 0 ; and silence it from complaining about said reg %C4 = -1 /u C1 %n0 = mul i8 %x, C3 %n1 = lshr i8 %n0, countTrailingZeros(C1) ; rotate right %n2 = shl i8 %n0, ((8-countTrailingZeros(C1)) %u 8) ; rotate right %n3 = or i8 %n1, %n2 ; rotate right %r = icmp ule i8 %n3, %C4 ``` https://rise4fun.com/Alive/oqd It kinda just works, really no weird edge-cases. But it isn't all that great for when comparing with non-zero. In particular, given `(X % C1) == C2`, there will be problems in the always-false tautological case where `C2 u>= C1`: https://rise4fun.com/Alive/pH3 That case is tautological, always-false: ``` Name: (X % Y) u>= Y %o0 = urem i8 %x, %y %r = icmp uge i8 %o0, %y => %r = false ``` https://rise4fun.com/Alive/ofu While we can't/shouldn't get such tautological case normally, we do deal with non-splat vectors, so unless we want to give up in this case, we need to fixup/short-circuit such lanes. There are two lowering variants: 1. We can blend between whatever computed result and the correct tautological result ``` Name: (X % C1) == C2 -> X * C3 <= C4 || false Pre: (C2 == 0 || C1 u<= C2) && (C1 u>> countTrailingZeros(C1)) * C3 == 1 %zz = and i8 C3, 0 ; trick alive into making C3 avaliable in precondition %o0 = urem i8 %x, C1 %r = icmp eq i8 %o0, C2 => %zz = and i8 C3, 0 ; and silence it from complaining about said reg %C4 = -1 /u C1 %n0 = mul i8 %x, C3 %n1 = lshr i8 %n0, countTrailingZeros(C1) ; rotate right %n2 = shl i8 %n0, ((8-countTrailingZeros(C1)) %u 8) ; rotate right %n3 = or i8 %n1, %n2 ; rotate right %is_tautologically_false = icmp ule i8 C1, C2 %res = icmp ule i8 %n3, %C4 %r = select i1 %is_tautologically_false, i1 0, i1 %res ``` https://rise4fun.com/Alive/PjT5 https://rise4fun.com/Alive/1KV 2. We can invert the comparison result ``` Name: (X % C1) == C2 -> X * C3 <= C4 || false Pre: (C2 == 0 || C1 u<= C2) && (C1 u>> countTrailingZeros(C1)) * C3 == 1 %zz = and i8 C3, 0 ; trick alive into making C3 avaliable in precondition %o0 = urem i8 %x, C1 %r = icmp eq i8 %o0, C2 => %zz = and i8 C3, 0 ; and silence it from complaining about said reg %C4 = -1 /u C1 %n0 = mul i8 %x, C3 %n1 = lshr i8 %n0, countTrailingZeros(C1) ; rotate right %n2 = shl i8 %n0, ((8-countTrailingZeros(C1)) %u 8) ; rotate right %n3 = or i8 %n1, %n2 ; rotate right %is_tautologically_false = icmp ule i8 C1, C2 %C4_fixed = select i1 %is_tautologically_false, i8 -1, i8 %C4 %res = icmp ule i8 %n3, %C4_fixed %r = xor i1 %res, %is_tautologically_false ``` https://rise4fun.com/Alive/2xC https://rise4fun.com/Alive/jpb5 3. We can expand into `and`/`or`: https://rise4fun.com/Alive/WGn https://rise4fun.com/Alive/lcb5 Blend-one is likely better since we avoid having to load the replacement from constant pool. `xor` is second best since it's still pretty general. I'm not adding `and`/`or` variants. Reviewers: RKSimon, craig.topper, spatel Reviewed By: RKSimon Subscribers: nick, hiraditya, xbolva00, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70051
This commit is contained in:
Roman Lebedev
parent
06e03bce80
commit
3f46022e33
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@ -4943,7 +4943,7 @@ SDValue TargetLowering::buildUREMEqFold(EVT SETCCVT, SDValue REMNode,
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ISD::CondCode Cond,
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DAGCombinerInfo &DCI,
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const SDLoc &DL) const {
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SmallVector<SDNode *, 2> Built;
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SmallVector<SDNode *, 4> Built;
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if (SDValue Folded = prepareUREMEqFold(SETCCVT, REMNode, CompTargetNode, Cond,
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DCI, DL, Built)) {
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for (SDNode *N : Built)
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@ -4978,26 +4978,40 @@ TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
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if (!isOperationLegalOrCustom(ISD::MUL, VT))
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return SDValue();
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// TODO: Could support comparing with non-zero too.
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ConstantSDNode *CompTarget = isConstOrConstSplat(CompTargetNode);
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if (!CompTarget || !CompTarget->isNullValue())
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return SDValue();
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bool HadOneDivisor = false;
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bool AllDivisorsAreOnes = true;
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bool HadTautologicalLanes = false;
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bool AllLanesAreTautological = true;
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bool HadEvenDivisor = false;
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bool AllDivisorsArePowerOfTwo = true;
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SmallVector<SDValue, 16> PAmts, KAmts, QAmts;
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bool HadTautologicalInvertedLanes = false;
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SmallVector<SDValue, 16> PAmts, KAmts, QAmts, IAmts;
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auto BuildUREMPattern = [&](ConstantSDNode *C) {
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auto BuildUREMPattern = [&](ConstantSDNode *CDiv, ConstantSDNode *CCmp) {
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// Division by 0 is UB. Leave it to be constant-folded elsewhere.
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if (C->isNullValue())
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if (CDiv->isNullValue())
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return false;
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const APInt &D = C->getAPIntValue();
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// If all divisors are ones, we will prefer to avoid the fold.
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HadOneDivisor |= D.isOneValue();
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AllDivisorsAreOnes &= D.isOneValue();
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const APInt &D = CDiv->getAPIntValue();
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const APInt &Cmp = CCmp->getAPIntValue();
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// x u% C1` is *always* less than C1. So given `x u% C1 == C2`,
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// if C2 is not less than C1, the comparison is always false.
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// But we will only be able to produce the comparison that will give the
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// opposive tautological answer. So this lane would need to be fixed up.
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bool TautologicalInvertedLane = D.ule(Cmp);
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HadTautologicalInvertedLanes |= TautologicalInvertedLane;
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// If we are checking that remainder is something smaller than the divisor,
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// then this comparison isn't tautological. For now this is not handled,
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// other than the comparison that remainder is zero.
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if (!Cmp.isNullValue() && !TautologicalInvertedLane)
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return false;
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// If all lanes are tautological (either all divisors are ones, or divisor
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// is not greater than the constant we are comparing with),
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// we will prefer to avoid the fold.
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bool TautologicalLane = D.isOneValue() || TautologicalInvertedLane;
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HadTautologicalLanes |= TautologicalLane;
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AllLanesAreTautological &= TautologicalLane;
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// Decompose D into D0 * 2^K
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unsigned K = D.countTrailingZeros();
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@ -5025,13 +5039,14 @@ TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
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assert(APInt::getAllOnesValue(ShSVT.getSizeInBits()).ugt(K) &&
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"We are expecting that K is always less than all-ones for ShSVT");
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// If the divisor is 1 the result can be constant-folded.
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if (D.isOneValue()) {
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// If the lane is tautological the result can be constant-folded.
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if (TautologicalLane) {
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// Set P and K amount to a bogus values so we can try to splat them.
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P = 0;
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K = -1;
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assert(Q.isAllOnesValue() &&
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"Expecting all-ones comparison for one divisor");
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// And ensure that comparison constant is tautological,
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// it will always compare true/false.
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Q = -1;
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}
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PAmts.push_back(DAG.getConstant(P, DL, SVT));
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@ -5045,11 +5060,11 @@ TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
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SDValue D = REMNode.getOperand(1);
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// Collect the values from each element.
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if (!ISD::matchUnaryPredicate(D, BuildUREMPattern))
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if (!ISD::matchBinaryPredicate(D, CompTargetNode, BuildUREMPattern))
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return SDValue();
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// If this is a urem by a one, avoid the fold since it can be constant-folded.
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if (AllDivisorsAreOnes)
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// If all lanes are tautological, the result can be constant-folded.
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if (AllLanesAreTautological)
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return SDValue();
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// If this is a urem by a powers-of-two, avoid the fold since it can be
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@ -5059,7 +5074,7 @@ TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
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SDValue PVal, KVal, QVal;
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if (VT.isVector()) {
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if (HadOneDivisor) {
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if (HadTautologicalLanes) {
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// Try to turn PAmts into a splat, since we don't care about the values
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// that are currently '0'. If we can't, just keep '0'`s.
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turnVectorIntoSplatVector(PAmts, isNullConstant);
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@ -5096,8 +5111,41 @@ TargetLowering::prepareUREMEqFold(EVT SETCCVT, SDValue REMNode,
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}
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// UREM: (setule/setugt (rotr (mul N, P), K), Q)
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return DAG.getSetCC(DL, SETCCVT, Op0, QVal,
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((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT));
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SDValue NewCC =
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DAG.getSetCC(DL, SETCCVT, Op0, QVal,
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((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT));
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if (!HadTautologicalInvertedLanes)
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return NewCC;
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// If any lanes previously compared always-false, the NewCC will give
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// always-true result for them, so we need to fixup those lanes.
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// Or the other way around for inequality predicate.
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assert(VT.isVector() && "Can/should only get here for vectors.");
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Created.push_back(NewCC.getNode());
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// x u% C1` is *always* less than C1. So given `x u% C1 == C2`,
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// if C2 is not less than C1, the comparison is always false.
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// But we have produced the comparison that will give the
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// opposive tautological answer. So these lanes would need to be fixed up.
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SDValue TautologicalInvertedChannels =
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DAG.getSetCC(DL, SETCCVT, D, CompTargetNode, ISD::SETULE);
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Created.push_back(TautologicalInvertedChannels.getNode());
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if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) {
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// If we have a vector select, let's replace the comparison results in the
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// affected lanes with the correct tautological result.
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SDValue Replacement = DAG.getBoolConstant(Cond == ISD::SETEQ ? false : true,
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DL, SETCCVT, SETCCVT);
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return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels,
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Replacement, NewCC);
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}
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// Else, we can just invert the comparison result in the appropriate lanes.
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if (isOperationLegalOrCustom(ISD::XOR, SETCCVT))
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return DAG.getNode(ISD::XOR, DL, SETCCVT, NewCC,
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TautologicalInvertedChannels);
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return SDValue(); // Don't know how to lower.
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}
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/// Given an ISD::SREM used only by an ISD::SETEQ or ISD::SETNE
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@ -22,23 +22,14 @@ define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI1_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI1_0]
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; CHECK-NEXT: adrp x8, .LCPI1_1
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI1_1]
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; CHECK-NEXT: adrp x8, .LCPI1_2
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; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI1_2]
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; CHECK-NEXT: adrp x8, .LCPI1_3
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; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI1_3]
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; CHECK-NEXT: adrp x8, .LCPI1_4
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; CHECK-NEXT: umull2 v5.2d, v0.4s, v1.4s
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; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s
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; CHECK-NEXT: neg v2.4s, v2.4s
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; CHECK-NEXT: uzp2 v1.4s, v1.4s, v5.4s
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; CHECK-NEXT: ldr q5, [x8, :lo12:.LCPI1_4]
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; CHECK-NEXT: ushl v1.4s, v1.4s, v2.4s
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; CHECK-NEXT: bsl v3.16b, v0.16b, v1.16b
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; CHECK-NEXT: mls v0.4s, v3.4s, v4.4s
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; CHECK-NEXT: cmeq v0.4s, v0.4s, v5.4s
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: dup v2.4s, w8
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; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: movi d1, #0xffff0000ffff0000
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; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>
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%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>
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@ -50,24 +41,14 @@ define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI2_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
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; CHECK-NEXT: adrp x8, .LCPI2_1
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI2_1]
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; CHECK-NEXT: adrp x8, .LCPI2_2
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; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI2_2]
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; CHECK-NEXT: adrp x8, .LCPI2_3
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; CHECK-NEXT: ldr q4, [x8, :lo12:.LCPI2_3]
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; CHECK-NEXT: adrp x8, .LCPI2_4
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; CHECK-NEXT: umull2 v5.2d, v0.4s, v1.4s
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; CHECK-NEXT: umull v1.2d, v0.2s, v1.2s
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; CHECK-NEXT: neg v2.4s, v2.4s
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; CHECK-NEXT: uzp2 v1.4s, v1.4s, v5.4s
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; CHECK-NEXT: ldr q5, [x8, :lo12:.LCPI2_4]
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; CHECK-NEXT: ushl v1.4s, v1.4s, v2.4s
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; CHECK-NEXT: bsl v3.16b, v0.16b, v1.16b
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; CHECK-NEXT: mls v0.4s, v3.4s, v4.4s
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; CHECK-NEXT: cmeq v0.4s, v0.4s, v5.4s
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; CHECK-NEXT: mvn v0.16b, v0.16b
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #43690, lsl #16
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; CHECK-NEXT: dup v2.4s, w8
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; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: movi d1, #0xffff0000ffff0000
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; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>
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%cmp = icmp ne <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>
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@ -79,25 +60,13 @@ define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI3_0
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
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; CHECK-NEXT: adrp x8, .LCPI3_1
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; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI3_1]
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; CHECK-NEXT: adrp x8, .LCPI3_2
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; CHECK-NEXT: umull2 v4.4s, v0.8h, v1.8h
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; CHECK-NEXT: umull v1.4s, v0.4h, v1.4h
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; CHECK-NEXT: uzp2 v1.8h, v1.8h, v4.8h
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; CHECK-NEXT: neg v3.8h, v3.8h
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; CHECK-NEXT: movi v2.2d, #0xffff00000000ffff
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; CHECK-NEXT: ushl v1.8h, v1.8h, v3.8h
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; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI3_2]
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; CHECK-NEXT: adrp x8, .LCPI3_3
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; CHECK-NEXT: movi v4.2d, #0x00ffffffff0000
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; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_3]
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; CHECK-NEXT: and v4.16b, v0.16b, v4.16b
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; CHECK-NEXT: orr v1.16b, v4.16b, v1.16b
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; CHECK-NEXT: mls v0.8h, v1.8h, v3.8h
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; CHECK-NEXT: cmeq v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: dup v2.8h, w8
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; CHECK-NEXT: mul v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: xtn v0.8b, v0.8h
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; CHECK-NEXT: movi d1, #0xffff0000ffff0000
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; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%urem = urem <8 x i16> %X, <i16 3, i16 1, i16 1, i16 9, i16 3, i16 1, i16 1, i16 9>
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%cmp = icmp eq <8 x i16> %urem, <i16 0, i16 0, i16 42, i16 42, i16 0, i16 0, i16 42, i16 42>
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@ -108,18 +77,19 @@ define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
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; CHECK-LABEL: t3_wide:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x9, #-6148914691236517206
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: adrp x11, .LCPI4_0
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; CHECK-NEXT: mov x8, v0.d[1]
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; CHECK-NEXT: movk x9, #43691
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; CHECK-NEXT: adrp x10, .LCPI4_0
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; CHECK-NEXT: umulh x9, x8, x9
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; CHECK-NEXT: ldr q0, [x10, :lo12:.LCPI4_0]
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; CHECK-NEXT: lsr x9, x9, #1
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; CHECK-NEXT: add x9, x9, x9, lsl #1
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; CHECK-NEXT: sub x8, x8, x9
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; CHECK-NEXT: movi v1.2d, #0000000000000000
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; CHECK-NEXT: mov v1.d[0], x8
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; CHECK-NEXT: cmeq v0.2d, v1.2d, v0.2d
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; CHECK-NEXT: fmov x10, d0
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; CHECK-NEXT: ldr q0, [x11, :lo12:.LCPI4_0]
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; CHECK-NEXT: mul x10, x10, x9
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; CHECK-NEXT: mul x8, x8, x9
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; CHECK-NEXT: fmov d1, x10
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; CHECK-NEXT: mov v1.d[1], x8
|
||||
; CHECK-NEXT: cmhs v0.2d, v0.2d, v1.2d
|
||||
; CHECK-NEXT: xtn v0.2s, v0.2d
|
||||
; CHECK-NEXT: movi d1, #0xffffffff00000000
|
||||
; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b
|
||||
; CHECK-NEXT: ret
|
||||
%urem = urem <2 x i64> %X, <i64 3, i64 1>
|
||||
%cmp = icmp eq <2 x i64> %urem, <i64 0, i64 42>
|
||||
|
|
|
|||
|
|
@ -25,94 +25,54 @@ define <4 x i1> @t0_all_tautological(<4 x i32> %X) nounwind {
|
|||
define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
|
||||
; CHECK-SSE2-LABEL: t1_all_odd_eq:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,0,0,954437177]
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
|
||||
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
|
||||
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
|
||||
; CHECK-SSE2-NEXT: psrld $1, %xmm2
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[3,3]
|
||||
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [3,1,1,9]
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[2,2,3,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm4
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm4
|
||||
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,2],xmm2[0,3]
|
||||
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[2,0,1,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm4
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
|
||||
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
|
||||
; CHECK-SSE2-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE41-LABEL: t1_all_odd_eq:
|
||||
; CHECK-SSE41: # %bb.0:
|
||||
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,0,0,954437177]
|
||||
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
|
||||
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
|
||||
; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1
|
||||
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
|
||||
; CHECK-SSE41-NEXT: psrld $1, %xmm1
|
||||
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
|
||||
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1
|
||||
; CHECK-SSE41-NEXT: psubd %xmm1, %xmm0
|
||||
; CHECK-SSE41-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1431655765,4294967295,4294967295,4294967295]
|
||||
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
|
||||
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
|
||||
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
|
||||
; CHECK-SSE41-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX1-LABEL: t1_all_odd_eq:
|
||||
; CHECK-AVX1: # %bb.0:
|
||||
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,0,0,954437177]
|
||||
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
|
||||
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
|
||||
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
|
||||
; CHECK-AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
|
||||
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
|
||||
; CHECK-AVX1-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX2-LABEL: t1_all_odd_eq:
|
||||
; CHECK-AVX2: # %bb.0:
|
||||
; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,0,0,954437177]
|
||||
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
|
||||
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
|
||||
; CHECK-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
|
||||
; CHECK-AVX2-NEXT: vpsrld $1, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm0[1,2],xmm1[3]
|
||||
; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
|
||||
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; CHECK-AVX2-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX512VL-LABEL: t1_all_odd_eq:
|
||||
; CHECK-AVX512VL: # %bb.0:
|
||||
; CHECK-AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,0,0,954437177]
|
||||
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
|
||||
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
|
||||
; CHECK-AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
|
||||
; CHECK-AVX512VL-NEXT: vpsrld $1, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm0[1,2],xmm1[3]
|
||||
; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; CHECK-AVX512VL-NEXT: retq
|
||||
%urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>
|
||||
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>
|
||||
|
|
@ -122,103 +82,60 @@ define <4 x i1> @t1_all_odd_eq(<4 x i32> %X) nounwind {
|
|||
define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
|
||||
; CHECK-SSE2-LABEL: t1_all_odd_ne:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,0,0,954437177]
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
|
||||
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,2,3,3]
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
|
||||
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
|
||||
; CHECK-SSE2-NEXT: psrld $1, %xmm2
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[3,3]
|
||||
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [3,1,1,9]
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[2,2,3,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm4
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm4[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm4
|
||||
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[1,2],xmm2[0,3]
|
||||
; CHECK-SSE2-NEXT: shufps {{.*#+}} xmm4 = xmm4[2,0,1,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm3, %xmm4
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm4[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
|
||||
; CHECK-SSE2-NEXT: psubd %xmm2, %xmm0
|
||||
; CHECK-SSE2-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm1
|
||||
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE41-LABEL: t1_all_odd_ne:
|
||||
; CHECK-SSE41: # %bb.0:
|
||||
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [2863311531,0,0,954437177]
|
||||
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
|
||||
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm3
|
||||
; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm1
|
||||
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3],xmm1[4,5],xmm3[6,7]
|
||||
; CHECK-SSE41-NEXT: psrld $1, %xmm1
|
||||
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
|
||||
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm1
|
||||
; CHECK-SSE41-NEXT: psubd %xmm1, %xmm0
|
||||
; CHECK-SSE41-NEXT: pcmpeqd {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [1431655765,4294967295,4294967295,4294967295]
|
||||
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
|
||||
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
|
||||
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm1
|
||||
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm0
|
||||
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
|
||||
; CHECK-SSE41-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX1-LABEL: t1_all_odd_ne:
|
||||
; CHECK-AVX1: # %bb.0:
|
||||
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,0,0,954437177]
|
||||
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
|
||||
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
|
||||
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
|
||||
; CHECK-AVX1-NEXT: vpsrld $1, %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3,4,5],xmm1[6,7]
|
||||
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
|
||||
; CHECK-AVX1-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX2-LABEL: t1_all_odd_ne:
|
||||
; CHECK-AVX2: # %bb.0:
|
||||
; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,0,0,954437177]
|
||||
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
|
||||
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
|
||||
; CHECK-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
|
||||
; CHECK-AVX2-NEXT: vpsrld $1, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm0[1,2],xmm1[3]
|
||||
; CHECK-AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [2863311531,2863311531,2863311531,2863311531]
|
||||
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; CHECK-AVX2-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX512VL-LABEL: t1_all_odd_ne:
|
||||
; CHECK-AVX512VL: # %bb.0:
|
||||
; CHECK-AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [2863311531,0,0,954437177]
|
||||
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[2,2,3,3]
|
||||
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm3, %xmm2
|
||||
; CHECK-AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
|
||||
; CHECK-AVX512VL-NEXT: vpsrld $1, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm0[1,2],xmm1[3]
|
||||
; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpcmpeqd {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; CHECK-AVX512VL-NEXT: retq
|
||||
%urem = urem <4 x i32> %X, <i32 3, i32 1, i32 1, i32 9>
|
||||
%cmp = icmp ne <4 x i32> %urem, <i32 0, i32 42, i32 0, i32 42>
|
||||
|
|
@ -228,72 +145,48 @@ define <4 x i1> @t1_all_odd_ne(<4 x i32> %X) nounwind {
|
|||
define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
|
||||
; CHECK-SSE2-LABEL: t2_narrow:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,0,0,65535,65535,0]
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
|
||||
; CHECK-SSE2-NEXT: pand %xmm1, %xmm2
|
||||
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm3 = [43691,0,0,58255,43691,0,0,58255]
|
||||
; CHECK-SSE2-NEXT: pmulhuw %xmm0, %xmm3
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm3, %xmm4
|
||||
; CHECK-SSE2-NEXT: psrlw $3, %xmm4
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,3,2,3]
|
||||
; CHECK-SSE2-NEXT: psrlw $1, %xmm3
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
|
||||
; CHECK-SSE2-NEXT: pandn %xmm3, %xmm1
|
||||
; CHECK-SSE2-NEXT: por %xmm2, %xmm1
|
||||
; CHECK-SSE2-NEXT: pmullw {{.*}}(%rip), %xmm1
|
||||
; CHECK-SSE2-NEXT: psubw %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: pcmpeqw {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: psubusw {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-SSE2-NEXT: pcmpeqw %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: pand {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE41-LABEL: t2_narrow:
|
||||
; CHECK-SSE41: # %bb.0:
|
||||
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [43691,0,0,58255,43691,0,0,58255]
|
||||
; CHECK-SSE41-NEXT: pmulhuw %xmm0, %xmm1
|
||||
; CHECK-SSE41-NEXT: movdqa %xmm1, %xmm2
|
||||
; CHECK-SSE41-NEXT: psrlw $3, %xmm2
|
||||
; CHECK-SSE41-NEXT: psrlw $1, %xmm1
|
||||
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
|
||||
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0],xmm0[1,2],xmm1[3,4],xmm0[5,6],xmm1[7]
|
||||
; CHECK-SSE41-NEXT: pmullw {{.*}}(%rip), %xmm1
|
||||
; CHECK-SSE41-NEXT: psubw %xmm1, %xmm0
|
||||
; CHECK-SSE41-NEXT: pcmpeqw {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [21845,65535,65535,65535,21845,65535,65535,65535]
|
||||
; CHECK-SSE41-NEXT: pminuw %xmm0, %xmm1
|
||||
; CHECK-SSE41-NEXT: pcmpeqw %xmm1, %xmm0
|
||||
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
|
||||
; CHECK-SSE41-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX1-LABEL: t2_narrow:
|
||||
; CHECK-AVX1: # %bb.0:
|
||||
; CHECK-AVX1-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpsrlw $3, %xmm1, %xmm2
|
||||
; CHECK-AVX1-NEXT: vpsrlw $1, %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
|
||||
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm0[1,2],xmm1[3,4],xmm0[5,6],xmm1[7]
|
||||
; CHECK-AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
|
||||
; CHECK-AVX1-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX2-LABEL: t2_narrow:
|
||||
; CHECK-AVX2: # %bb.0:
|
||||
; CHECK-AVX2-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpsrlw $3, %xmm1, %xmm2
|
||||
; CHECK-AVX2-NEXT: vpsrlw $1, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
|
||||
; CHECK-AVX2-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm0[1,2],xmm1[3,4],xmm0[5,6],xmm1[7]
|
||||
; CHECK-AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpsubw %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; CHECK-AVX2-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX512VL-LABEL: t2_narrow:
|
||||
; CHECK-AVX512VL: # %bb.0:
|
||||
; CHECK-AVX512VL-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpsrlw $3, %xmm1, %xmm2
|
||||
; CHECK-AVX512VL-NEXT: vpsrlw $1, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
|
||||
; CHECK-AVX512VL-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm0[1,2],xmm1[3,4],xmm0[5,6],xmm1[7]
|
||||
; CHECK-AVX512VL-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpsubw %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpcmpeqw {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]
|
||||
; CHECK-AVX512VL-NEXT: retq
|
||||
%urem = urem <8 x i16> %X, <i16 3, i16 1, i16 1, i16 9, i16 3, i16 1, i16 1, i16 9>
|
||||
%cmp = icmp eq <8 x i16> %urem, <i16 0, i16 0, i16 42, i16 42, i16 0, i16 0, i16 42, i16 42>
|
||||
|
|
@ -301,46 +194,81 @@ define <8 x i1> @t2_narrow(<8 x i16> %X) nounwind {
|
|||
}
|
||||
|
||||
define <2 x i1> @t3_wide(<2 x i64> %X) nounwind {
|
||||
; CHECK-SSE2-LABEL: t3_wide:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movq %xmm0, %rcx
|
||||
; CHECK-SSE2-NEXT: movabsq $-6148914691236517205, %rdx # imm = 0xAAAAAAAAAAAAAAAB
|
||||
; CHECK-SSE2-NEXT: movq %rcx, %rax
|
||||
; CHECK-SSE2-NEXT: mulq %rdx
|
||||
; CHECK-SSE2-NEXT: shrq %rdx
|
||||
; CHECK-SSE2-NEXT: leaq (%rdx,%rdx,2), %rax
|
||||
; CHECK-SSE2-NEXT: subq %rax, %rcx
|
||||
; CHECK-SSE2-NEXT: movq %rcx, %xmm1
|
||||
; CHECK-SSE2-NEXT: pcmpeqd {{.*}}(%rip), %xmm1
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm1[1,0,3,2]
|
||||
; CHECK-SSE2-NEXT: pand %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
; CHECK-SSE-LABEL: t3_wide:
|
||||
; CHECK-SSE: # %bb.0:
|
||||
; CHECK-SSE-NEXT: movdqa {{.*#+}} xmm1 = [12297829382473034411,12297829382473034411]
|
||||
; CHECK-SSE-NEXT: movdqa %xmm0, %xmm2
|
||||
; CHECK-SSE-NEXT: pmuludq %xmm1, %xmm2
|
||||
; CHECK-SSE-NEXT: movdqa %xmm0, %xmm3
|
||||
; CHECK-SSE-NEXT: psrlq $32, %xmm3
|
||||
; CHECK-SSE-NEXT: pmuludq %xmm1, %xmm3
|
||||
; CHECK-SSE-NEXT: pmuludq {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE-NEXT: paddq %xmm3, %xmm0
|
||||
; CHECK-SSE-NEXT: psllq $32, %xmm0
|
||||
; CHECK-SSE-NEXT: paddq %xmm2, %xmm0
|
||||
; CHECK-SSE-NEXT: pxor {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE-NEXT: movdqa {{.*#+}} xmm1 = [15372286730238776661,9223372034707292159]
|
||||
; CHECK-SSE-NEXT: movdqa %xmm0, %xmm2
|
||||
; CHECK-SSE-NEXT: pcmpgtd %xmm1, %xmm2
|
||||
; CHECK-SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,0,2,2]
|
||||
; CHECK-SSE-NEXT: pcmpeqd %xmm1, %xmm0
|
||||
; CHECK-SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
|
||||
; CHECK-SSE-NEXT: pand %xmm3, %xmm0
|
||||
; CHECK-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
|
||||
; CHECK-SSE-NEXT: por %xmm0, %xmm1
|
||||
; CHECK-SSE-NEXT: pcmpeqd %xmm0, %xmm0
|
||||
; CHECK-SSE-NEXT: pxor %xmm1, %xmm0
|
||||
; CHECK-SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero
|
||||
; CHECK-SSE-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE41-LABEL: t3_wide:
|
||||
; CHECK-SSE41: # %bb.0:
|
||||
; CHECK-SSE41-NEXT: movq %xmm0, %rcx
|
||||
; CHECK-SSE41-NEXT: movabsq $-6148914691236517205, %rdx # imm = 0xAAAAAAAAAAAAAAAB
|
||||
; CHECK-SSE41-NEXT: movq %rcx, %rax
|
||||
; CHECK-SSE41-NEXT: mulq %rdx
|
||||
; CHECK-SSE41-NEXT: shrq %rdx
|
||||
; CHECK-SSE41-NEXT: leaq (%rdx,%rdx,2), %rax
|
||||
; CHECK-SSE41-NEXT: subq %rax, %rcx
|
||||
; CHECK-SSE41-NEXT: movq %rcx, %xmm0
|
||||
; CHECK-SSE41-NEXT: pcmpeqq {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE41-NEXT: retq
|
||||
; CHECK-AVX1-LABEL: t3_wide:
|
||||
; CHECK-AVX1: # %bb.0:
|
||||
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [12297829382473034411,12297829382473034411]
|
||||
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
|
||||
; CHECK-AVX1-NEXT: vpsrlq $32, %xmm0, %xmm3
|
||||
; CHECK-AVX1-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpsllq $32, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpaddq %xmm0, %xmm2, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
|
||||
; CHECK-AVX1-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX-LABEL: t3_wide:
|
||||
; CHECK-AVX: # %bb.0:
|
||||
; CHECK-AVX-NEXT: vmovq %xmm0, %rcx
|
||||
; CHECK-AVX-NEXT: movabsq $-6148914691236517205, %rdx # imm = 0xAAAAAAAAAAAAAAAB
|
||||
; CHECK-AVX-NEXT: movq %rcx, %rax
|
||||
; CHECK-AVX-NEXT: mulq %rdx
|
||||
; CHECK-AVX-NEXT: shrq %rdx
|
||||
; CHECK-AVX-NEXT: leaq (%rdx,%rdx,2), %rax
|
||||
; CHECK-AVX-NEXT: subq %rax, %rcx
|
||||
; CHECK-AVX-NEXT: vmovq %rcx, %xmm0
|
||||
; CHECK-AVX-NEXT: vpcmpeqq {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: retq
|
||||
; CHECK-AVX2-LABEL: t3_wide:
|
||||
; CHECK-AVX2: # %bb.0:
|
||||
; CHECK-AVX2-NEXT: vmovdqa {{.*#+}} xmm1 = [12297829382473034411,12297829382473034411]
|
||||
; CHECK-AVX2-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
|
||||
; CHECK-AVX2-NEXT: vpsrlq $32, %xmm0, %xmm3
|
||||
; CHECK-AVX2-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpsllq $32, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpcmpgtq {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
|
||||
; CHECK-AVX2-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX512VL-LABEL: t3_wide:
|
||||
; CHECK-AVX512VL: # %bb.0:
|
||||
; CHECK-AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [12297829382473034411,12297829382473034411]
|
||||
; CHECK-AVX512VL-NEXT: vpmuludq %xmm1, %xmm0, %xmm2
|
||||
; CHECK-AVX512VL-NEXT: vpsrlq $32, %xmm0, %xmm3
|
||||
; CHECK-AVX512VL-NEXT: vpmuludq %xmm1, %xmm3, %xmm1
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||||
; CHECK-AVX512VL-NEXT: vpmuludq {{.*}}(%rip), %xmm0, %xmm0
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||||
; CHECK-AVX512VL-NEXT: vpaddq %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpsllq $32, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpaddq %xmm0, %xmm2, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpminuq {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpcmpeqq %xmm1, %xmm0, %xmm0
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||||
; CHECK-AVX512VL-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero
|
||||
; CHECK-AVX512VL-NEXT: retq
|
||||
%urem = urem <2 x i64> %X, <i64 3, i64 1>
|
||||
%cmp = icmp eq <2 x i64> %urem, <i64 0, i64 42>
|
||||
ret <2 x i1> %cmp
|
||||
|
|
|
|||
Loading…
Reference in New Issue