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[GlobalISel] Fix typo Extact to Extract in function name. NFC.

This commit is contained in:
Jay Foad 2022-01-07 11:04:25 +00:00
parent ae29d5a484
commit 3f3fe4a5cf
6 changed files with 10 additions and 10 deletions
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2
llvm/include/llvm/CodeGen/TargetLowering.h
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@ -1838,7 +1838,7 @@ public:
virtual Function *getSSPStackGuardCheck(const Module &M) const;
/// \returns true if a constant G_UBFX is legal on the target.
virtual bool isConstantUnsignedBitfieldExtactLegal(unsigned Opc, LLT Ty1,
virtual bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
LLT Ty2) const {
return false;
}

4
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
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@ -4127,7 +4127,7 @@ bool CombinerHelper::matchBitfieldExtractFromAnd(
assert(MI.getOpcode() == TargetOpcode::G_AND);
Register Dst = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(Dst);
if (!getTargetLowering().isConstantUnsignedBitfieldExtactLegal(
if (!getTargetLowering().isConstantUnsignedBitfieldExtractLegal(
TargetOpcode::G_UBFX, Ty, Ty))
return false;
@ -4214,7 +4214,7 @@ bool CombinerHelper::matchBitfieldExtractFromShrAnd(
const Register Dst = MI.getOperand(0).getReg();
LLT Ty = MRI.getType(Dst);
if (!getTargetLowering().isConstantUnsignedBitfieldExtactLegal(
if (!getTargetLowering().isConstantUnsignedBitfieldExtractLegal(
TargetOpcode::G_UBFX, Ty, Ty))
return false;

2
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -19776,7 +19776,7 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
Op, OriginalDemandedBits, OriginalDemandedElts, Known, TLO, Depth);
}
bool AArch64TargetLowering::isConstantUnsignedBitfieldExtactLegal(
bool AArch64TargetLowering::isConstantUnsignedBitfieldExtractLegal(
unsigned Opc, LLT Ty1, LLT Ty2) const {
return Ty1 == Ty2 && (Ty1 == LLT::scalar(32) || Ty1 == LLT::scalar(64));
}

2
llvm/lib/Target/AArch64/AArch64ISelLowering.h
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@ -1136,7 +1136,7 @@ private:
// with BITCAST used otherwise.
SDValue getSVESafeBitCast(EVT VT, SDValue Op, SelectionDAG &DAG) const;
bool isConstantUnsignedBitfieldExtactLegal(unsigned Opc, LLT Ty1,
bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
LLT Ty2) const override;
};

2
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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@ -4904,7 +4904,7 @@ AMDGPUTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
}
}
bool AMDGPUTargetLowering::isConstantUnsignedBitfieldExtactLegal(
bool AMDGPUTargetLowering::isConstantUnsignedBitfieldExtractLegal(
unsigned Opc, LLT Ty1, LLT Ty2) const {
return Ty1 == Ty2 && (Ty1 == LLT::scalar(32) || Ty1 == LLT::scalar(64));
}

2
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
View File

@ -335,7 +335,7 @@ public:
AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
bool isConstantUnsignedBitfieldExtactLegal(unsigned Opc, LLT Ty1,
bool isConstantUnsignedBitfieldExtractLegal(unsigned Opc, LLT Ty1,
LLT Ty2) const override;
};