forked from OSchip/llvm-project
[RISCV][NFC] Remove tailing whitespaces in RISCVInstrInfoVSDPatterns.td and RISCVInstrInfoVVLPatterns.td
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@ -368,22 +368,22 @@ multiclass VPatWidenBinarySDNode_VV_VX_WV_WX<SDNode op, PatFrags extop, string i
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def : Pat<(op (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
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(vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
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(!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX)
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vti.Vti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
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vti.Vti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
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vti.Vti.AVL, vti.Vti.Log2SEW)>;
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def : Pat<(op (vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
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(vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
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(!cast<Instruction>(instruction_name#"_VX_"#vti.Vti.LMul.MX)
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vti.Vti.RegClass:$rs2, GPR:$rs1,
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vti.Vti.RegClass:$rs2, GPR:$rs1,
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vti.Vti.AVL, vti.Vti.Log2SEW)>;
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def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
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(vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
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(!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX)
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vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
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vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
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vti.Vti.AVL, vti.Vti.Log2SEW)>;
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def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
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(vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
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(!cast<Instruction>(instruction_name#"_WX_"#vti.Vti.LMul.MX)
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vti.Wti.RegClass:$rs2, GPR:$rs1,
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vti.Wti.RegClass:$rs2, GPR:$rs1,
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vti.Vti.AVL, vti.Vti.Log2SEW)>;
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}
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}
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@ -418,12 +418,12 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
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def : Pat<(op (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
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(vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
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(!cast<Instruction>(instruction_name#"_VV_"#vti.Vti.LMul.MX)
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vti.Vti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
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vti.Vti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
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vti.Vti.AVL, vti.Vti.Log2SEW)>;
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def : Pat<(op (vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs2))),
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(vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector (SplatPat vti.Vti.ScalarRegClass:$rs1))))),
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(!cast<Instruction>(instruction_name#"_V"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
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vti.Vti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
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vti.Vti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
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vti.Vti.AVL, vti.Vti.Log2SEW)>;
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}
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}
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@ -433,12 +433,12 @@ multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> {
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def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
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(vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
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(!cast<Instruction>(instruction_name#"_WV_"#vti.Vti.LMul.MX)
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vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
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vti.Wti.RegClass:$rs2, vti.Vti.RegClass:$rs1,
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vti.Vti.AVL, vti.Vti.Log2SEW)>;
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def : Pat<(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
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(vti.Wti.Vector (fpext_oneuse (vti.Vti.Vector (SplatPat vti.Vti.ScalarRegClass:$rs1))))),
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(!cast<Instruction>(instruction_name#"_W"#vti.Vti.ScalarSuffix#"_"#vti.Vti.LMul.MX)
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vti.Wti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
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vti.Wti.RegClass:$rs2, vti.Vti.ScalarRegClass:$rs1,
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vti.Vti.AVL, vti.Vti.Log2SEW)>;
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}
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}
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@ -616,7 +616,7 @@ multiclass VPatReductionVL<SDNode vop, string instruction_name, bit is_float> {
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multiclass VPatBinarySDNodeExt_V_WV<SDNode op, PatFrags extop, string instruction_name> {
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foreach vti = AllWidenableIntVectors in {
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def : Pat<
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(vti.Vti.Vector
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(vti.Vti.Vector
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(riscv_trunc_vector_vl
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(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
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(vti.Wti.Vector (extop (vti.Vti.Vector vti.Vti.RegClass:$rs1)))),
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@ -631,7 +631,7 @@ multiclass VPatBinarySDNodeExt_V_WV<SDNode op, PatFrags extop, string instructio
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multiclass VPatBinarySDNodeExt_V_WX<SDNode op, PatFrags extop, string instruction_name> {
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foreach vti = AllWidenableIntVectors in {
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def : Pat<
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(vti.Vti.Vector
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(vti.Vti.Vector
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(riscv_trunc_vector_vl
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(op (vti.Wti.Vector vti.Wti.RegClass:$rs2),
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(vti.Wti.Vector (extop (vti.Vti.Vector (SplatPat GPR:$rs1))))),
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